■ DESCRIPTION The MB91101 and MB91101A are a standard single-chip microcontroller constructed around the 32-bit RISC CPU (FR* family) core with abundant I/O resources and bus control functions optimized for high-performance/high-speed CPU processing for embedded controller applications. To support the vast memory space accessed by the 32-bit CPU, the MB91101 and MB91101A normally operate in the external bus access mode and executes instructions on the internal 1 Kbyte cache memory and 2 Kbytes RAM for enhanced performance. The MB91101 and MB91101A are optimized for applications requiring high-performance CPU processing such as navigation systems, high-performance FAXs and printer controllers. ■ FEATURES FR CPU • 32-bit RISC, load/store architecture, 5-stage pipeline • Operating clock frequency: Internal 50 MHz/external 25 MHz (PLL used at source oscillation 12.5 MHz) • General purpose registers: 32 bits × 16 • 16-bit fixed length instructions (basic instructions), 1 instruction/1 cycle • Memory to memory transfer, bit processing, barrel shifter processing: Optimized for embedded applications • Function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages • Register interlock functions, efficient assembly language coding • Branch instructions with delay slots: Reduced overhead time in branch executions • Internal multiplier/supported at instruction level Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles • Interrupt (push PC and PS): 6 cycles, 16 priority levels External bus interface • Clock doubler: Internal 50 MHz, external bus 25 MHz operation • 25-bit address bus (32 Mbytes memory space) • 8/16-bit data bus • Basic external bus cycle: 2 clock cycles • Chip select outputs for setting down to a minimum memory block size of 64 Kbytes: 6 • Interface supported for various memory technologies DRAM interface (area 4 and 5) • Automatic wait cycle insertion: Flexible setting, from 0 to 7 for each area • Unused data/address pins can be configured as input/output ports. • Little endian mode supported (Select 1 area from area 1 to 5) DRAM interface • 2 banks independent control (area 4 and 5) • Normal mode (double CAS DRAM)/high-speed page mode (single CAS DRAM)/Hyper DRAM • Basic bus cycle: Normally 5 cycles, 2-cycle access possible in high-speed page mode • Programmable waveform: Automatic 1-cycle wait insertion to RAS and CAS cycles • DRAM refresh CBR refresh (interval time configurable by 6-bit timer) Self-refresh mode • Supports 8/9/10/12-bit column address width • 2CAS/1WE, 2WE/1CAS selective Cache memory • 1-Kbyte instruction cache memory • 32 block/way, 4 entry(4 word)/block • 2 way set associative • Lock function: For specific program code to be resident in cashe memory DMA controller (DMAC) • 8 channels • Transfer incident/external pins/internal resource interrupt requests • Transfer sequence: Step transfer/block transfer/burst transfer/continuous transfer • Transfer data length: 8 bits/16 bits/32 bits selective • NMI/interrupt request enables temporary stop operation. UART • 3 independent channels • Full-duplex double buffer • Data length: 7 bits to 9 bits (non-parity), 6 bits to 8 bits (parity) • Asynchronous (start-stop system), CLK-synchronized communication selective • Multi-processor mode • Internal 16-bit timer (U-TIMER) operating as a proprietary baud rate generator: Generates any given baud rate • External clock can be used as a transfer clock. • Error detection: Parity, frame, overrun (Continued)
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