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M2S56D40AKT-75AL 데이터시트 (PDF) - Mitsubishi Electric Semiconductor

M2S56D40AKT-75AL Datasheet PDF - Mitsubishi Electric Semiconductor
부품명 M2S56D40AKT-75AL
다운로드  M2S56D40AKT-75AL 다운로드

파일 크기   824.58 Kbytes
페이지   37 Pages
제조업체  MITSUBISHI [Mitsubishi Electric Semiconductor]
홈페이지  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor
상세설명 256M Double Data Rate Synchronous DRAM

M2S56D40AKT-75AL Datasheet (PDF)

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M2S56D40AKT-75AL Datasheet PDF - Mitsubishi Electric Semiconductor

부품명 M2S56D40AKT-75AL
다운로드  M2S56D40AKT-75AL Click to download

파일 크기   824.58 Kbytes
페이지   37 Pages
제조업체  MITSUBISHI [Mitsubishi Electric Semiconductor]
홈페이지  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor
상세설명 256M Double Data Rate Synchronous DRAM

M2S56D40AKT-75AL 데이터시트 (HTML) - Mitsubishi Electric Semiconductor

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M2S56D40AKT-75AL 제품 세부 정보

DESCRIPTION
M2S56D20AKT is a 4-bank x 16,777,216-word x 4-bit,
M2S56D30AKT is a 4-bank x 8,388,608-word x 8-bit,
M2S56D40AKT is a 4-bank x 4,194,304-word x 16-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The M2S56D20/30/40AKT achieves very high speed data rate up to 133MHz, and are suitable for main memory in computer systems.

FEATURES
- Vdd=Vddq=2.5V+0.2V
- Double data rate architecture; two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transitions edges of DQS
- Commands entered on each positive CLK edge;
- data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- SSTL_2 Interface
- 400-mil, 66-pin Thin Small Outline Package (TSOP II)
- JEDEC standard



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