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ATPL230A 데이터시트(PDF) 103 Page - ATMEL Corporation |
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ATPL230A 데이터시트(HTML) 103 Page - ATMEL Corporation |
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103 / 122 page ![]() 103 ATPL230A [DATASHEET] Atmel-43053J-ATPL230A-Datasheet_22-Sep-16 9.3.8 Other Registers 9.3.8.1 System Configuration Register Name: SYS_CONFIG Address: 0xFE2C Access: Read/Write Reset: 0x04 • CONV_PD: Converter Power Down Microcontroller can activate internal converter power down mode by setting this bit. When internal converter is in power down mode, the system is unable to receive. This bit is high-level active. • PHY_RST: Physical Layer Reset This bit resets the Physical layer. To perform a Physical layer reset cycle, microcontroller must set this bit to ‘1’ and then must clear it to ‘0’. 76543210 --- - CONV_PD - - PHY_RST |
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