16F819 datasheet(101/176 Pages) MICROCHIP

101 / 176 page

 2004 Microchip Technology Inc.

DS39598E-page 99

PIC16F818/819

12.13 Power-Down Mode (Sleep)

Power-Down mode is entered by executing a SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit (Status<3>) is cleared, the

TO (Status<4>) bit is set and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, low or high-impedance).

For lowest current consumption in this mode, place all

I/O pins at either VDD or VSS, ensure no external cir-

cuitry is drawing current from the I/O pin, power-down

the A/D and disable external clocks. Pull all I/O pins

that are high-impedance inputs, high or low externally,

to avoid switching currents caused by floating inputs.

The T0CKI input should also be at VDD or VSS for

lowest current consumption. The contribution from

on-chip pull-ups on PORTB should also be considered.

The MCLR pin must be at a logic high level (VIHMC).

12.13.1

WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of the

following events:

External Reset input on MCLR pin.

Watchdog

Timer

wake-up

(if

WDT

was

enabled).

Interrupt from INT pin, RB port change or a

peripheral interrupt.

External MCLR Reset will cause a device Reset. All

other events are considered a continuation of program

execution and cause a “wake-up”. The TO and PD bits

in the Status register can be used to determine the

cause of the device Reset. The PD bit, which is set on

power-up, is cleared when Sleep is invoked. The TO bit

is cleared if a WDT time-out occurred and caused

wake-up.

The following peripheral interrupts can wake the device

from Sleep:

TMR1 interrupt. Timer1 must be operating as an

asynchronous counter.

CCP Capture mode interrupt.

Special event trigger (Timer1 in Asynchronous

mode using an external clock).

SSP (Start/Stop) bit detect interrupt.

SSP transmit or receive in Slave mode (SPI/I2C).

A/D conversion (when A/D clock source is RC).

EEPROM write operation completion.

Other peripherals cannot generate interrupts since

during Sleep, no on-chip clocks are present.

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up

occurs regardless of the state of the GIE bit. If the GIE

bit is clear (disabled), the device continues execution at

the instruction after the SLEEP instruction. If the GIE bit

is set (enabled), the device executes the instruction

after the SLEEP instruction and then branches to the

interrupt address (0004h). In cases

where the

execution of the instruction following SLEEP is not

desirable, the user should have a NOP after the SLEEP

instruction.

12.13.2

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEP

instruction, the SLEEP instruction will

complete as a NOP. Therefore, the WDT and WDT

postscaler will not be cleared, the TO bit will not

be set and PD bit will not be cleared.

• If the interrupt occurs during or after the

execution of a SLEEP instruction, the device will

immediately wake-up from Sleep. The SLEEP

instruction will be completely executed before the

wake-up. Therefore, the WDT and WDT

postscaler will be cleared, the TO bit will be set

and the PD bit will be cleared.

Even if the flag bits were checked before executing a

SLEEP

instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

To ensure that the WDT is cleared, a CLRWDT instruction

should be executed before a SLEEP instruction.

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