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ST72F521M 데이터시트(PDF) 191 Page - STMicroelectronics

부품명 ST72F521M
상세설명  8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
PDF  199 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72F521M 데이터시트(HTML) 191 Page - STMicroelectronics

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ST72521M/R/AR
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14 ST72521M/(A)R DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (ROM). FLASH devices are
shipped to customers with a default content, while
ROM factory coded parts contain the code sup-
plied by the customer. This implies that FLASH de-
vices have to be configured by the customer using
the Option Bytes while the ROM devices are facto-
ry-configured.
14.1 FLASH OPTION BYTES
The option bytes allow the hardware configuration
of the microcontroller to be selected. They have no
address in the memory map and can be accessed
only in programming mode (for example using a
standard ST7 programming tool). The default con-
tent of the FLASH is fixed to FFh. To program the
FLASH devices directly using ICP, FLASH devices
are shipped to customers with the internal RC
clock source. In masked ROM devices, the option
bytes are fixed in hardware by the ROM code (see
option list).
OPTION BYTE 0
OPT7= WDG HALT
Watchdog and HALT mode
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
OPT6= WDG SW
Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT5 = CSS
Clock security system on/off
This option bit enables or disables the clock secu-
rity system function (CSS) which includes the
clock filter and the backup safe oscillator.
0: CSS enabled
1: CSS disabled
OPT4:3= VD[1:0]
Voltage detection
These option bits enable the voltage detection
block (LVD, and AVD) with a selected threshold for
the LVD and AVD (EVD+AVD).
Note: For details on the AVD and LVD threshold
levels refer to Section 12.3.2 on page 157
STATIC OPTION BYTE 0
70
STATIC OPTION BYTE 1
70
WDG
VD
OSCTYPE
OSCRANGE
10
10
2
10
Default
1
1100
1
1
11
1
1
0
1
1
1
1
Selected Low Voltage Detector
VD1
VD0
LVD and AVD Off
1
1
Not Used (Lowest Threshold: (VDD~3V)
1
0
Not Used (Med. Threshold VDD~3.5V)
0
1
Highest Voltage Threshold (VDD~4V)
0
0



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