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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AT89C5131A-RDTIL 데이터시트(PDF) 174 Page - ATMEL Corporation |
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AT89C5131A-RDTIL 데이터시트(HTML) 174 Page - ATMEL Corporation |
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174 / 184 page  174 AT89C5131A-L 4338F–USB–08/07 Timings Test conditions: capacitive load on all pins= 50 pF. Table 128. SPI Interface Master AC Timing VDD = 2.7 to 5.5 V, TA = -40 to +85°C Note: TPER is XTAL period when SPI interface operates in X2 mode or twice XTAL period when SPI inter- face operates in X1 mode. Symbol Parameter Min Max Unit Slave Mode T CHCH Clock Period 2 T PER T CHCX Clock High Time 0.8 T PER T CLCX Clock Low Time 0.8 T PER T SLCH, TSLCL SS Low to Clock edge 100 ns T IVCL, TIVCH Input Data Valid to Clock Edge 50 ns T CLIX, TCHIX Input Data Hold after Clock Edge 50 ns T CLOV, TCHOV Output Data Valid after Clock Edge 50 ns T CLOX, TCHOX Output Data Hold Time after Clock Edge 0 ns T CLSH, TCHSH SS High after Clock Edge 0 ns T SLOV SS Low to Output Data Valid 4T PER+20 ns T SHOX Output Data Hold after SS High 2T PER+100 ns T SHSL SS High to SS Low 2T PER+120 T ILIH Input Rise Time 2 µ s T IHIL Input Fall Time 2 µ s T OLOH Output Rise time 100 ns T OHOL Output Fall Time 100 ns Master Mode T CHCH Clock Period 4 T PER T CHCX Clock High Time 2T PER-20 ns T CLCX Clock Low Time 2T PER-20 ns T IVCL, TIVCH Input Data Valid to Clock Edge 50 ns T CLIX, TCHIX Input Data Hold after Clock Edge 50 ns T CLOV, TCHOV Output Data Valid after Clock Edge 20 ns T CLOX, TCHOX Output Data Hold Time after Clock Edge 0 ns |
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