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PIC18F4520E/MLQTP 데이터시트(PDF) 183 Page - Microchip Technology

부품명 PIC18F4520E/MLQTP
상세설명  28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PDF  390 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
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PIC18F4520E/MLQTP 데이터시트(HTML) 183 Page - Microchip Technology

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 2004 Microchip Technology Inc.
Preliminary
DS39631A-page 181
PIC18F2420/2520/4420/4520
17.4.4.5
Clock Synchronization and
the CKP bit
When the CKP bit is cleared, the SCL output is forced
to ‘0’. However, clearing the CKP bit will not assert the
SCL output low until the SCL output is already sam-
pled low. Therefore, the CKP bit will not assert the
SCL line until an external I2C master device has
already asserted the SCL line. The SCL output will
remain low until the CKP bit is set and all other
devices on the I2C bus have deasserted SCL. This
ensures that a write to the CKP bit will not violate the
minimum
high
time
requirement
for
SCL
(see
Figure 17-12).
FIGURE 17-12:
CLOCK SYNCHRONIZATION TIMING
SDA
SCL
DX – 1
DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON
CKP
Master device
deasserts clock
Master device
asserts clock



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