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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MB86391 데이터시트(PDF) 9 Page - Fujitsu Component Limited. |
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MB86391 데이터시트(HTML) 9 Page - Fujitsu Component Limited. |
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9 / 69 page  FUJITSU LIMITED Proprietary and Confidential MB86391 12, November 2001 Product Specification Rev. 1.1 5 1.4 Block Diagram Fig. 1.4 shows a block outline diagram of this LSI and Table 1.4 lists the functional overviews of major blocks. Fig. 1.4 : MB86391 block diagram Table 1.4 : Overview of major block functions Block name Functional overview Video encoder Encodes video data input from the TBC controller to create video streams. Audio encoder Encodes audio data input from outside to create audio streams. Multiplexer Multiplexes video and audio streams generated by video and audio encoders to generate 8bit parallel stream data for output to outside. Controller Controls the entire MB86391 using dedicated firmware. TBC controller Stores video data input from outside in an external SDRAM and theninput it to the video encoder. The TBC (Time Base Corrector) function is accomplished by buffering video data in the SDRAM. Host/SDRAM interface controller Arbitrates SDRAM and MB86391 internal register access requests from MB86391 internal blocks and external master devices. Also used as the command interface with the host. Serial interface controller Downloads dedicated firmware to the external SDRAM via this interface at the time of serial booting. Also used as a command interface with the host. Video PES converter Converts the format of video streams the video encoder has generated and outputs to the multiplexer. DMA controller Controls DMA transfer among MB86391 blocks and external SDRAMs. Boot ROM Stores the boot program for the internal controller. Video encoder Audio encoder Controller (32bit RISC processor) Multiplexer TBC controller Serial interface controller Boot ROM Host/SDRAM interface controller SRAM (8k ×8) MB86391 Serial interface Host/SDRAM interface Video encoding SDRAM interface Audio input interface Video input interface Bit stream output port PLL Clock input (27MHz) 27MHz 54MHz |
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