STR720 datasheet(142/401 Pages) STMICROELECTRONICS

142 / 401 page

STR720 - RESET AND CLOCK CONTROL UNIT (RCCU)

142/401

13.3.3.2 Idle mode

If SLOW bit in CLKCTL register is ’0’, then a low frequency internal clock, (PLLREFCLK/32),

could be used, setting IDLE bit to ’1’, as source clock for AHB clock and APB, ATAPI

prescalers reference clock. IDLE mode can be used when a low power consumption is

needed, but no CLK_AF is available as external low frequency clock source.

13.3.3.3 SLOW mode

When active (SLOW bit = ’1’) the external CLK_AF low frequency clock source is selected as

system clock. (refer also to Idle mode)

13.3.3.4 STOP mode

A STOP mode is provided, where all clocks are stopped, while power supply is maintained to

the whole chip. STOP mode is entered only if STOP_EN bit inside MSKCTL register has been

written to ’1’. In this case STOP input driven active (high) causes the RCCU to stretch all

system clocks.

Normal operation may be resumed by an external event, connected to STOP input (refer to

WIU specification). After wake-up, operations resume from previous state without any loss of

information.

WARNING: All low power modes are completely under software control via the proper

configuration of the RCCU registers.

Figure 17. Clock Control unit programming

1/2

CLK

CLK_AF

PLL

Clock Multiplier

Unit

/Divider

APB_CLK

AHB_CLK

1/2, 1/4

1/32

ATAPI_CLK

CLK_AF

(32 kHz)

DIV2

PLLBYP

SLOW

IDLE

nSTOP

1/8, 1/16

1/2, 1/3

STOP_EN

PLLCLKREF

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