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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STR720 데이터시트(PDF) 189 Page - STMicroelectronics |
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STR720 데이터시트(HTML) 189 Page - STMicroelectronics |
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189 / 401 page  STR720 - BUFFERED SPI (BSPI) 189/401 Figure 25. BSPI Clocking Scheme (CPOL=0, CPHA=0) Figure 26. BSPI Clocking Scheme (CPOL=0, CPHA=1) CPOL=0, CPHA=0 SS Internal Strobe for Data Capture on positive edge of SCK MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB Internal Strobe for Data Capture on positive edge of SCK Data captured on MOSI (in) MISO (out) Data captured on MISO (in) MOSI (out) SCK (out) SCK (in) MASTER SIGNALS SLAVE SIGNALS CPOL=0, CPHA=1 SS Internal Strobe for Data Capture on negative edge of SCK MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB Internal Strobe for Data Capture on negative edge of SCK MISO (out) MOSI (out) SCK (out) SCK (in) Data captured on MISO (in) Data captured on MOSI (in) MASTER SIGNALS SLAVE SIGNALS 1 |
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