STR720 datasheet(201/401 Pages) STMICROELECTRONICS

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STR720 - BUFFERED SPI (BSPI)

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BSPI Receive Register (BSPRXR)

Address Offset: 00h

Reset value: 0000h

Bits 15:0 = RX[15:0]: Received data.

This register contains the data received from the BSPI bus. If the FIFO is disabled then the

data from the shift register is placed into the receive register directly. If the FIFO is enabled

then the received data is transferred into the FIFO. In sixteen bit mode all the register bits are

utilized. In eight bit reception mode the received data is replicated on the upper and lower

eight bits of the register so to support both little and big endian memory systems.

17.4.1

A summary overview of the BSPI registers is given in the following table.

(*)Data is justified depending on transmission mode, Bit 15 = MSB.

Refer to Table 20 on page 49 for the base address.

16 bit Reception

RX[15:0]

8 bit Reception

RX[7:0]

Table 47. BSPI Register Map

Addr.

Offset

Name

9876543210

BSPRXR

RX[15:0] (*)

BSPTXR

TX[15:0] (*)

BSPCSR1

RFE[3:0]

WL[1:0]

CPHA

CPOL

BEIE

Reserved

REIE

RIE[1:0]

MSTR

BSPE

BSPCSR2

TIE[1:0]

TFE[3:0]

TFNE

TFF

TUFL

TFE

ROFL

RFF

RFNE

BERR

Res.

DFIFO

BSPCLK

Reserved

DIV[7:0]

BSPCSR3

Reserved

RREQ

_EN

TREQ_

RBURST_

LEN[1:0]

TBURST_

LEN [1:0]

DMA

_EN

MASK

_SS

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