STM32MP157DAC1 datasheet(157/258 Pages) STMICROELECTRONICS

157 / 258 page

DS12504 Rev 2

157/258

STM32MP157A

Electrical characteristics

238

PLL3_800, PLL4_800 characteristics

Jitter

RMS cycle-to-

cycle jitter

fPLL_P_Q_R_OUT division = 1

to 16

Without Fractional mode

VCO = 400 MHz

18(3)

±ps

VCO = 533 MHz

14(3)

VCO = 800 MHz

12(3)

fPLL_P_Q_R_OUT division = 1

to 16

With Fractional mode

VCO = 533 MHz

20(3)

VCO = 800 MHz

18(3)

RMS period jitter

fPLL_P_Q_R_OUT division = 1

to 16

Without Fractional mode

VCO = 400 MHz

16(3)

±ps

VCO = 533 MHz

12(3)

VCO = 800 MHz

10(3)

fPLL_P_Q_R_OUT division = 1

to 16

With Fractional mode

VCO = 533 MHz

16(3)

VCO = 800 MHz

15(3)

Long term jitter

fPLL_P_Q_R_OUT division = 1

to 16

fPLL_IN = 8 MHz

Without Fractional mode

VCO = 400 MHz

225(4)

VCO = 533 MHz

200(4)

VCO = 800 MHz

100(4)

fPLL_P_Q_R_OUT division = 1

to 16

fPLL_IN = 8 MHz

With Fractional mode

VCO = 400 MHz

350(4)

VCO = 533 MHz

250(4)

VCO = 800 MHz

150(4)

IVDD_PLL(2)

PLL power

consumption on

VDD_PLL (Analog)

VCO freq = 800 MHz

930

µA

VCO freq = 400 MHz

560

IVDDCORE(2)

PLL power

consumption on

VDDCORE (Digital)

VCO freq = 800 MHz

4200

μA

VCO freq = 400 MHz

2100

1. Guaranteed by design unless otherwise specified.

2. Guaranteed by characterization results.

3. Measured on DDR high speed IO.

4. Measured on DDR high speed IO for 10000 output clock cycles.

Table 39. PLL1_1600, PLL2_1600 characteristics(1) (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 40. PLL3_800, PLL4_800 characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fPLL_IN

PLL input clock

Normal mode

MHz

Sigma delta mode

PLL input clock

duty cycle

-10

STM32MP157DAC1 데이터시트(PDF) 157 Page - STMicroelectronics

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