ST7FDALIF2M6 datasheet(103/141 Pages) STMICROELECTRONICS

103 / 141 page

ST7DALI

103/141

13.3.2 Operating Conditions with Low Voltage Detector (LVD)

TA = -40 to 85°C, unless otherwise specified

Note:

1. Not tested in production.

2. Not tested in production. The VDD rise time rate condition is needed to insure a correct device power-on and LVD reset.

When the VDD slope is outside these values, the LVD may not ensure a proper reset of the MCU.

13.3.3 Auxiliary Voltage Detector (AVD) Thresholds

TA = -40 to 85°C, unless otherwise specified

Note:

1. Not tested in production.

13.3.4 Internal RC Oscillator and PLL

The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte).

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIT+(LVD)

Reset release threshold

(VDD rise)

High Threshold

Med. Threshold

Low Threshold

4.001)

3.40 1)

2.65 1)

4.25

3.60

2.90

4.50

3.80

3.15

VIT-(LVD)

Reset generation threshold

(VDD fall)

High Threshold

Med. Threshold

Low Threshold

3.80

3.20

2.40

4.05

3.40

2.70

4.30 1)

3.65 1)

2.901)

Vhys

LVD voltage threshold hysteresis

VIT+(LVD)-VIT-(LVD)

200

VtPOR

VDD rise time rate

20000

µs/V

tg(VDD)

Filtered glitch delay on VDD

Not detected by the LVD

150

IDD(LVD)

LVD/AVD current consumption

220

µA

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIT+(AVD)

1=>0 AVDF flag toggle threshold

(VDD rise)

High Threshold

Med. Threshold

Low Threshold

4.401)

3.901)

3.201)

4.70

4.10

3.40

5.00

4.30

3.60

VIT-(AVD)

0=>1 AVDF flag toggle threshold

(VDD fall)

High Threshold

Med. Threshold

Low Threshold

4.30

3.70

2.90

4.60

3.90

3.20

4.901)

4.101)

3.401)

Vhys

AVD voltage threshold hysteresis

VIT+(AVD)-VIT-(AVD)

150

∆V

IT-

Voltage drop between AVD flag set

and LVD reset activation

VDD fall

0.45

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDD(RC)

Internal RC Oscillator operating voltage

2.4

5.5

VDD(x4PLL) x4 PLL operating voltage

2.4

3.3

VDD(x8PLL)

x8 PLL operating voltage

3.3

5.5

tSTARTUP

PLL Startup time

PLL

input

clock

(fPLL)

cycles

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