AM652X datasheet(244/277 Pages) TI1

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244

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019

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Detailed Description

6.4

Other Subsystems

6.4.1

DMSC

Integrated in WKUP domain Device Management and Security Controller (WKUP_DMSC) provides control

over the device boot sequencing, device management, power management, and security. With the

factory-sealed firmware, DMSC main functions include:

•

Device management

•

On-chip power management and wake-up control

•

Device boot configuration and sequence

•

Secure boot setup

•

Authentication routines (all modes), including R5F island only boot modes

•

Decryption routines

•

Firewall control for isolation and Security

•

Runtime Security Management and resource allocation

•

Arm Cortex-M3 based DMSC acts as system security master and protects critical security assets

during run-time. As part of booting on High Security (HS) device, DMSC uses on-chip keys to establish

root-of-trust and authenticate images to reinforce trust. DMSC controls the power management of

device, hence is responsible to bring device cleanly out of reset and enforce clock and reset rules.

DMSC power management functions are critical to bring device to low power modes and sense

wakeup events to bring device back to active state. DMSC acts also as main boot processor and as

such is the very first subsystem that is brought out of reset after device power-on-reset.

For more information, see WKUP Device Management and Security Controller (DMSC) section in the

device TRM.

6.4.2

MSMC

The

Multicore

Shared

Memory

Controller

(MSMC)

forms

the

heart

the

compute

cluster

(COMPUTE_CLUSTER0) providing high-bandwidth resource access both to and from all of the connected

processing elements and the rest of the system. MSMC serves as the data-movement backbone of the

compute cluster.

For more information, see Multicore Shared Memory Controller (MSMC) section in the device TRM.

6.4.3

NAVSS

6.4.3.1

NAVSS0

Main SoC Navigator Subsystem (NAVSS0) consists of DMA/Queue Management components – UDMA

and Ring Accelerator (UDMASS), Peripherals (Module subsystem [MODSS]), and a North Bridge (NBSS).

UDMASS – UDMASS is the essential part of the DMA Architecture. UDMASS consists of:

•

Unified DMA Controller

•

Ring Accelerator

•

Packet Streaming Interface (PSI-L)

MODSS – MODSS is a collection of peripherals with different system-level functions, for example,

interprocessor communication and time sync, among others. NAVSS0 contains the following modules:

•

Mailbox

•

Spinlock

•

Two Timer Managers (Timer banks)

•

Time Stamp Module (CPTS)

•

Memory CRC module

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