XRT7250 datasheet(220/463 Pages) EXAR

220 / 463 page

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DS3/E3 FRAMER IC

XRT7250

REV. 1.1.1

201

NOTES:

1. The white (e.g., unshaded) boxes reflect tasks that

the user’s system must perform in order to config-

ure the Receive FEAC Processor to receive FEAC

messages.

2. A brief description of the steps that must exist

within the FEAC Validation and FEAC Removal

Interrupt Service Routines exists in Section 3.6

4.3.3.2

The Message Oriented Signaling (e.g.,

LAP-D) Processing via the Receive DS3 HDLC

Controller block

The LAPD Receiver (within the Receive DS3 HDLC

Controller block) allows the user to receive PMDL

messages from the remote terminal equipment, via

the inbound DS3 frames. In this case, the inbound

message bits will be carried by the 3 DL bit-fields of

F-Frame 5, within each DS3 M-Frame. The remote

LAPD Transmitter will transmit a LAPD Message to

the Near-End Receiver via these three bits within

each DS3 Frame. The LAPD Receiver will receive

and store the information portion of the received

LAPD frame into the Receive LAPD Message Buffer,

which is located at addresses: 0xDE through 0x135

within the on-chip RAM. The LAPD Receiver has the

following responsibilities.

• Framing to the incoming LAPD Messages

• Filtering out stuffed 0s (within the information pay-

load)

• Storing the Frame Message into the Receive LAPD

Message Buffer

• Perform Frame Check Sequence (FCS) Verification

• Provide status indicators for

End of Message (EOM)

Flag Sequence Byte detected

Abort Sequence detected

Message Type

C/R Type

The occurrence of FCS Errors

FIGURE 84. FLOW DIAGRAM DEPICTING HOW THE RECEIVE FEAC PROCESSOR FUNCTIONS

START

ENABLE THE “FEAC REMOVAL AND

“VALIDATION” INTERRUPTS.

This is accomplished by writing “xxxx 1010” into the

“RxDS3 FEAC Interrupt/Status Register (Address = 0x17)

ENABLE THE “FEAC REMOVAL AND

“VALIDATION” INTERRUPTS.

This is accomplished by writing “xxxx 1010” into the

“RxDS3 FEAC Interrupt/Status Register (Address = 0x17)

RECEIVE FEAC PROCESSOR BEGINS READING IN

THE FEAC BIT-FIELDS (OF INCOMING DS3 FRAMES)

The Receive FEAC Processor checks for the “FEAC Framing

Alignment” pattern of “01111110”.

RECEIVE FEAC PROCESSOR BEGINS READING IN

THE FEAC BIT-FIELDS (OF INCOMING DS3 FRAMES)

The Receive FEAC Processor checks for the “FEAC Framing

Alignment” pattern of “01111110”.

Is the

“FEAC Framing

Alignment”pattern

present in the FEAC

Channel

Is the

“FEAC Framing

Alignment”pattern

present in the FEAC

Channel

READ IN THE “6-BIT FEAC CODE WORD”

The 6-bit FEAC Code Word immediately follows the “FEAC

Framing Alignment” Pattern.

READ IN THE “6-BIT FEAC CODE WORD”

The 6-bit FEAC Code Word immediately follows the “FEAC

Framing Alignment” Pattern.

Has this

same FEAC

Code Word been

Received in 8 out of the last

10 FEAC Message

Receptions?

Has this

same FEAC

Code Word been

Received in 8 out of the last

10 FEAC Message

Receptions?

Has a FEAC

Code Word (other than

the last “Validated Code Word)

been Received in 3 out of the last

10 FEAC Message

Receptions?

Has a FEAC

Code Word (other than

the last “Validated Code Word)

been Received in 3 out of the last

10 FEAC Message

Receptions?

GENERATE “FEAC

VALIDATION” INTERRUPT

GENERATE “FEAC

VALIDATION” INTERRUPT

INVOKE “FEAC VALIDATION”

INTERRUPTSERVICE ROUTINE.

INVOKE “FEAC VALIDATION”

INTERRUPTSERVICE ROUTINE.

GENERATE “FEAC

REMOVAL” INTERRUPT

GENERATE “FEAC

REMOVAL” INTERRUPT

INVOKE “FEAC REMOVAL”

INTERRUPTSERVICE ROUTINE.

INVOKE “FEAC REMOVAL”

INTERRUPTSERVICE ROUTINE.

YES

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