| 전자부품 데이터시트 검색엔진 |
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XRT7250 데이터시트(PDF) 260 Page - Exar Corporation |
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XRT7250 데이터시트(HTML) 260 Page - Exar Corporation |
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260 / 463 page ![]() áç áç áç áç XRT7250 DS3/E3 FRAMER IC REV. 1.1.1 241 How to configure the XRT7250 into the Serial/ Loop-Timed/Non-Overhead Interface Mode 1. Set the NibIntf input pin "Low". 2. Set the TimRefSel[1:0] bit fields (within the Framer Operating Mode Register) to "00", as illustrated below. 3. Interface the XRT7250, to the Terminal Equip- ment, as illustrated in Figure 100. 5.2.1.2 Mode 2 - The Serial/Local-Timed/ Frame-Slave Mode Behavior of the XRT7250 If the XRT7250 has been configured to operate in this mode, then the XRT7250 will function as follows. A. Local-Timed - Uses the TxInClk signal as the Timing Reference In this mode, the Transmit Section of the XRT7250 will use the TxInClk signal as its timing reference. B. Serial Mode The XRT7250 will receive the E3 payload data, in a serial manner, via the TxSer input pin. The Transmit Payload Data Input Interface (within the XRT7250) will latch this data into its circuitry, on the rising edge of the TxInClk input clock signal. FIGURE 101. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT7250 TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK AND THE TERMINAL EQUIPMENT (FOR MODE 1 OPERATION) Terminal Equipment Signals E3_Clock_In E3_Data_Out Tx_Start_of_Frame E3_Overhead_Ind XRT7250 Transmit Payload Data I/F Signals RxOutClk TxSer TxFrame TxOH_Ind Payload[1522] Payload[1523] FAS, Bit 9 FAS, Bit 8 Payload[1522] Payload[1523] FAS, Bit 9 FAS, Bit 8 Note: The FAS pattern will not be processed by the Transmit Payload Data Input Interface. E3 Frame Number N E3 Frame Number N + 1 Note: TxFrame pulses high to denote E3 Frame Boundary. Note: TxOH_Ind pulses high for 12 bit periods in order to denote Overhead Data (e.g., the FAS pattern and the A & N bits). FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) BIT 7BIT 6BIT 5BIT 4BIT 3BIT2 BIT 1 BIT 0 Local Loopback DS3/E3* Internal LOS Enable RESET Interrupt Enable Reset Frame Format TimRefSel[1:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0101 0 0 0 |
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