XRT7250 datasheet(268/463 Pages) EXAR

268 / 463 page

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XRT7250

DS3/E3 FRAMER IC

REV. 1.1.1

249

Mode 5 Operation of the Terminal Equipment

In Figure 108 both the Terminal Equipment and the

XRT7250 will be driven by an external 8.592MHz

clock signal. The Terminal Equipment will receive the

8.592MHz clock signal via the E3_Nib_Clock_In input

pin. The XRT7250 will output the 8.592MHz clock

signal via the TxNibClk output pin.

The Terminal Equipment will serially output the data

on the E3_Data_Out[3:0] pins, upon the rising edge

of the signal at the E3_Clock_In input pin.

NOTE: The E3_Data_Out[3:0] output pins of the Terminal

Equipment is electrically connected to the TxNib[3:0] input

pins.

The XRT7250 will latch the data, residing on the Tx-

Nib[3:0] input pins, on the rising edge of the TxNibClk

signal.

In this case, the Terminal Equipment has the respon-

sibility of providing the framing reference signal by

pulsing the Tx_Start_of_Frame output pin (and in

turn, the TxFrameRef input pin of the XRT7250)

"High" for one bit-period, coincident with the first bit of

a new E3 frame. Once the XRT7250 detects the ris-

ing edge of the input at its TxFrameRef input pin, it

will begin generation of a new E3 frame.

Finally, the XRT7250 will always internally generate

the Overhead bits, when it is operating in both the E3

and Nibble-parallel modes. The XRT7250 will pull the

TxOHInd input pin "Low".

The behavior of the signals between the XRT7250

and the Terminal Equipment for E3 Mode 5 Operation

is illustrated in Figure 109.

FIGURE 108. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA

INPUT INTERFACE BLOCK OF THE XRT7250 FOR MODE 5 (NIBBLE-PARALLEL/LOCAL-TIMED/FRAME-SLAVE) OPERA-

TION

Terminal Equipment

XRT7250 E3 Framer

E3_Data_Out[3:0]

E3_Nib_Clock_In

Tx_Start_of_Frame

TxNib[3:0]

TxNibClk

TxFrameRef

NibInt

VCC

34.368MHz Clock Source

TxInClk

8.592MHz

E3_Overhead_Ind

TxOH_Ind

XRT7250 데이터시트(PDF) 268 Page - Exar Corporation

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