XRT7250 datasheet(408/463 Pages) EXAR

408 / 463 page

áç

XRT7250

DS3/E3 FRAMER IC

REV. 1.1.1

389

6.3.1.2.3

Line Code Violations

The Receive E3 LIU Interface block will also check

the incoming E3 data stream for line code violations.

For example, when the Receive E3 LIU Interface

block detects a valid bipolar violation (e.g., in HDB3

line code), it will substitute four zeros into the binary

data stream. However, if the bipolar violation is in-

valid, then an LCV (Line Code Violation) is flagged

and the PMON LCV Event Count Register (Address =

0x50 and 0x51) will also be incremented. Additional-

ly, the LCV-One-Second Accumulation Registers

(Address = 0x6E and 0x6F) will be incremented. For

example: If the incoming E3 data is HDB3 encoded,

the Receive E3 LIU Interface block will also increment

the LCV One-Second Accumulation Register if three

(or more) consecutive zeros are received.

6.3.1.2.4

RxLineClk Clock Edge Selection

The incoming unipolar or bipolar data, applied to the

RxPOS and the RxNEG input pins are clocked into

the Receive E3 LIU Interface block via the RxLineClk

signal. The Framer IC allows the user to specify

which edge (e.g, rising or falling) of the RxLineClk

signal will sample and latch the signal at the RxPOS

and RxNEG input signals into the Framer IC. The us-

er can make this selection by writing the appropriate

data to bit 1 of the I/O Control Register, as depicted

below.

Table 84 depicts the relationship between the value of

this bit-field to the sampling clock edge of RxLineClk.

Figure 191 and Figure 192 present the Waveform and

Timing Relationships between RxLineClk, RxPOS

and RxNEG for each of these configurations.

II/O CONTROL REGISTER (ADDRESS = 0X01)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT2

BIT 1BIT 0

Disable

TxLOC

LOC

Disable

RxLOC

AMI/ZeroSup*

Unipolar/

Bipolar*

TxLine CLK

Invert

RxLine CLK

Invert

Reframe

R/W

0100

TABLE 84: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REGISTER,

AND THE SAMPLING EDGE OF THE

RXLINECLK SIGNAL

RXCLKINV

(BIT 1)

RESULT

.Rising Edge:

RxPOS and RxNEG are sampled at the rising edge of RxLineClk. See Figure 191 for timing relationship

between RxLineClk, RxPOS, and RxNEG.

Falling Edge:

RxPOS and RxNEG are sampled at the falling edge of RxLineClk. See Figure 192 for timing relationship

between RxLineClk, RxPOS, and RxNEG.

XRT7250 데이터시트(PDF) 408 Page - Exar Corporation

XRT7250 데이터시트(HTML) 408 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL