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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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IS25LP032D-RKLA3 데이터시트(PDF) 102 Page - Integrated Silicon Solution, Inc |
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IS25LP032D-RKLA3 데이터시트(HTML) 102 Page - Integrated Silicon Solution, Inc |
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102 / 118 page  IS25LP032D IS25WP032D Integrated Silicon Solution, Inc.- www.issi.com 102 Rev. A12 08/04/2020 9.6 AC CHARACTERISTICS (Under operating range, refer to section 9.4 for AC measurement conditions) Symbol Parameter Min Typ(2) Max Units fCT Clock Frequency except for fast read Quad I/O, QPI, DTR and read (03h) 0 133 MHz Clock Frequency for fast read Quad I/O and QPI IS25LP 0 133 IS25WP 0 104 Clock Frequency for fast read DTR: SPI DTR, Dual DTR, Dual I/O DTR, Quad I/O DTR, and QPI DTR. 0 66 MHz fC Clock Frequency for read (03h) 0 50 MHz tCLCH(1) SCK Rise Time (peak to peak) 0.1 V/ns tCHCL(1) SCK Fall Time ( peak to peak) 0.1 V/ns tCKH SCK High Time For read (03h) 0.45 x 1/fCmax ns For others 0.45 x 1/fCTmax tCKL SCK Low Time For read (03h) 0.45 x 1/fCmax ns For others 0.45 x 1/fCTmax tCEH CE# High Time 7 ns tCS CE# Active Setup Time 5 ns tCH CE# Active Hold Time 5 ns tCHSL CE# Not Active Hold Time 2.7 ns tSHCH CE# Not Active Setup Time 2.7 ns tDS Data In Setup Time STR 2 ns DTR 1.5 tDH Data in Hold Time STR 2 ns DTR 1.5 tV Output Valid @ 133MHz (CL = 15pF) 7 ns @ 104MHz (CL = 30pF) 8 tOH Output Hold Time 2 ns tDIS(1) Output Disable Time 8 ns tWHSL(3) Write Protect Setup Time 20 ns tSHWL(3) Write Protect Hold Time 100 ns tHLCH HOLD Active Setup Time relative to SCK 2 ns tCHHH HOLD Active Hold Time relative to SCK 2 ns tHHCH HOLD Not Active Setup Time relative to SCK 2 ns tCHHL HOLD Not Active Hold Time relative to SCK 2 ns tLZ(1) HOLD to Output Low Z 12 ns tHZ(1) HOLD to Output High Z 12 ns tEC Sector Erase Time (4Kbyte) 70 300 ms Block Erase Time (32Kbyte) 0.1 0.5 s Block Erase time (64Kbyte) 0.15 1.0 s Chip Erase Time (32Mb) 8 24 s tPP Page Program Time 0.2 0.8 ms |
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