ST7LITE3 datasheet(153/167 Pages) STMICROELECTRONICS

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ST7LITE3

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13.11 10-BIT ADC CHARACTERISTICS

Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.

Notes:

1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-

lines and are not tested.

2. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.

3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance g(reater than10k

Ω).

Data based on characterization results, not tested in production.

4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then

always valid.

Figure 101. Typical Application with ADC

Symbol

Parameter

Conditions

Min

Typ 1)

Max

Unit

fADC

ADC clock frequency

0.5

MHz

VAIN

Conversion voltage range 2)

VSSA

VDDA

RAIN

External input resistor

10 3)

Ω

CADC

Internal sample and hold capacitor

tSTAB

Stabilization time after ADC enable

fCPU=8MHz, fADC=4MHz

0 4)

µs

tADC

Conversion time (Sample+Hold)

3.5

- Sample capacitor loading time

- Hold conversion time

1/fADC

AINx

ST72XXX

VDD

±1

µA

0.6V

CADC

VAIN

RAIN

10-Bit A/D

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