| 전자부품 데이터시트 검색엔진 |
|
STM32MP157F 데이터시트(PDF) 194 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STM32MP157F 데이터시트(HTML) 194 Page - STMicroelectronics |
|
194 / 260 page ![]() Electrical characteristics STM32MP157C/F 194/260 DS12505 Rev 5 Figure 37. QUADSPI timing diagram - SDR mode Figure 38. QUADSPI timing diagram - DDR mode Table 74. QUADSPI characteristics in DDR mode Symbol Parameter Conditions Min Typ Max Unit Fck1/t(CLK) QUADSPI clock frequency 2.7 V < VDD < 3.6 V CL=20 pF -- 90 MHz 1.71 V < VDD < 3.6 V CL=15 pF -- 90 tw(CLKH) QUADSPI clock high and low time -t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5 ns tw(CLKL) -t(CLK)/2 - 0.5 - t(CLK)/2 + 0.5 tsr(IN), tsf(IN) Data input setup time - 0.5 - - thr(IN), thf(IN) Data input hold time - 2.75 - - tvr(OUT), tvf(OUT) Data output valid time DHHC = 0 - 1 1.5 DHHC = 1 Pres = 1, 2... -t(CLK)/4+1 t(CLK)/4+1.5 thr(OUT), thf(OUT) Data output hold time DHHC = 0 0 - - DHHC = 1 Pres = 1, 2... t(CLK)/4 - - MSv36878V2 Data output IO0 IO1 IO2 Clock Data input IO0 IO1 IO2 t(CLK) tw(CLKH) tw(CLKL) tr(CLK) tf(CLK) ts(IN) th(IN) tv(OUT) th(OUT) MSv36879V3 Data output IO0 IO2 IO4 Clock Data input IO0 IO2 IO4 t(CLK) tw(CLKH) tw(CLKL) tr(CLK) tf(CLK) tsf(IN) thf(IN) tvf(OUT) thr(OUT) IO1 IO3 IO5 IO1 IO3 IO5 tvr(OUT) thf(OUT) tsr(IN) thr(IN) |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |