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PCIMX6QP5AVT2AB 데이터시트(PDF) 117 Page - NXP Semiconductors |
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PCIMX6QP5AVT2AB 데이터시트(HTML) 117 Page - NXP Semiconductors |
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117 / 160 page ![]() Electrical Characteristics i.MX 6DualPlus/6QuadPlus Applications Processors Industrial Products, Rev. 3, 11/2018 NXP Semiconductors 117 Figure 82. Test Access Port Timing Diagram Figure 83. JTAG_TRST_B Timing Diagram Table 70. JTAG Timing ID Parameter1,2 All Frequencies Unit Min Max SJ0 JTAG_TCK frequency of operation 1/(3xTDC) 1 0.001 22 MHz SJ1 JTAG_TCK cycle time in crystal mode 45 — ns SJ2 JTAG_TCK clock pulse width measured at VM 2 22.5 — ns SJ3 JTAG_TCK rise and fall times — 3 ns SJ4 Boundary scan input data set-up time 5 — ns SJ5 Boundary scan input data hold time 24 — ns SJ6 JTAG_TCK low to output data valid — 40 ns SJ7 JTAG_TCK low to output high impedance — 40 ns SJ8 JTAG_TMS, JTAG_TDI data set-up time 5 — ns JTAG_TCK (Input) JTAG_TDI (Input) JTAG_TDO (Output) JTAG_TDO (Output) JTAG_TDO (Output) VIH VIL Input Data Valid Output Data Valid Output Data Valid JTAG_TMS SJ8 SJ9 SJ10 SJ11 SJ10 JTAG_TCK (Input) (Input) SJ13 SJ12 JTAG_TRST_B |
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