EDB8164B4PR-1DITF-R datasheet(129/152 Pages) MICRON

129 / 152 page

Cycle Time Derating for Core Timing Parameters

For a given number of clocks (tnPARAM), when tCK(avg) and tERR(tnPARAM),act exceed

tERR(tnPARAM),allowed, cycle time derating may be required for core timing parame-

ters.

CycleTimeDerating = max

tPARAM +tERR(tnPARAM),act – tERR(tnPARAM),allowed

– tCK(avg) , 0

tnPARAM

Cycle time derating analysis should be conducted for each core timing parameter. The

amount of cycle time derating required is the maximum of the cycle time deratings de-

termined for each individual core timing parameter.

Clock Cycle Derating for Core Timing Parameters

For each core timing parameter and a given number of clocks (tnPARAM), clock cycle

derating should be specified with tJIT(per).

For a given number of clocks (tnPARAM), when tCK(avg) plus (tERR(tnPARAM),act) ex-

ceed the supported cumulative tERR(tnPARAM),allowed, derating is required. If the

equation below results in a positive value for a core timing parameter (tCORE), the re-

quired clock cycle derating will be that positive value (in clocks).

ClockCycleDerating = RU

tPARAM + tERR(tnPARAM),act – tERR(tnPARAM),allowed

– tnPARAM

tCK(avg)

Cycle-time derating analysis should be conducted for each core timing parameter.

Clock Jitter Effects on Command/Address Timing Parameters

Command/address timing parameters (tIS, tIH, tISCKE, tIHCKE, tISb, tIHb, tISCKEb,

tIHCKEb) are measured from a command/address signal (CKE, CS_n, or CA[9:0]) transi-

tion edge to its respective clock signal (CK_t/CK_c) crossing. The specification values

are not affected by the tJIT(per) applied, because the setup and hold times are relative to

the clock signal crossing that latches the command/address. Regardless of clock jitter

values, these values must be met.

Clock Jitter Effects on READ Timing Parameters

tRPRE

When the device is operated with input clock jitter, tRPRE must be derated by the

tJIT(per),act,max of the input clock that exceeds tJIT(per),allowed,max. Output derat-

ings are relative to the input clock:

tRPRE(min,derated) = 0.9 –

tJIT(per),act,max – tJIT(per),allowed,max

tCK(avg)

For example, if the measured jitter into a LPDDR2-800 device has tCK(avg) = 2500ps,

tJIT(per),act,min = –172ps, and tJIT(per),act,max = +193ps, then tRPRE,min,derated =

0.9 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (193 - 100)/2500 =

0.8628 tCK(avg).

tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS)

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Clock Period Jitter

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

129

Micron Technology, Inc. reserves the right to change products or specifications without notice.

EDB8164B4PR-1DITF-R 데이터시트(PDF) 129 Page - Micron Technology

EDB8164B4PR-1DITF-R 데이터시트(HTML) 129 Page - Micron Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL