EDB8164B4PR-1DITF-R datasheet(136/152 Pages) MICRON

136 / 152 page

Table 91: AC Timing (Continued)

Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul-

tiples of tCK) as well as the timing specifications when values for both are indicated.

Parameter

Symbol

Min/

Max

tCK

Min

Data Rate

Unit Notes

1066

933

800

667

533

400

333

tDQSCK derating

tDQSCK

(derated)

MAX

–

5620

6000 6000 6000 6000 6000 6000

Core timing temperature

derating

tRCD

(derated)

MIN

–

tRCD + 1.875

tRC

(derated)

MIN

–

tRC + 1.875

tRAS

(derated)

MIN

–

tRAS + 1.875

tRP

(derated)

MIN

–

tRP + 1.875

tRRD

(derated)

MIN

–

tRRD + 1.875

Notes:

1. Frequency values are for reference only. Clock cycle time (tCK) is used to determine de-

vice capabilities.

2. All AC timings assume an input slew rate of 1 V/ns.

3. READ, WRITE, and input setup and hold values are referenced to VREF.

4. tDQSCKDS is the absolute value of the difference between any two tDQSCK measure-

ments (in a byte lane) within a contiguous sequence of bursts in a 160ns rolling window.

tDQSCKDS is not tested and is guaranteed by design. Temperature drift in the system is

<10˚C/s. Values do not include clock jitter.

5. tDQSCKDM is the absolute value of the difference between any two tDQSCK measure-

ments (in a byte lane) within a 1.6

μs rolling window. tDQSCKDM is not tested and is

guaranteed by design. Temperature drift in the system is <10˚C/s. Values do not include

clock jitter.

6. tDQSCKDL is the absolute value of the difference between any two tDQSCK measure-

ments (in a byte lane) within a 32ms rolling window. tDQSCKDL is not tested and is

guaranteed by design. Temperature drift in the system is <10˚C/s. Values do not include

clock jitter.

For LOW-to-HIGH and HIGH-to-LOW transitions, the timing reference is at the point

when the signal crosses the transition threshold (VTT). tHZ and tLZ transitions occur in

the same access time (with respect to clock) as valid data transitions. These parameters

are not referenced to a specific voltage level but to the time when the device output is

no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ)), or begins driving (for tRPRE,

tLZ(DQS), tLZ(DQ)). The figure below shows a method to calculate the point when the

device is no longer driving tHZ(DQS) and tHZ(DQ) or begins driving tLZ(DQS) and tLZ(DQ)

by measuring the signal at two different voltages. The actual voltage measurement

points are not critical as long as the calculation is consistent. The parameters tLZ(DQS),

tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The timing parameters

tRPRE and tRPST are determined from the differential signal DQS_t/DQS_c.

Output Transition Timing

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

AC Timing

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

136

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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