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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32H750VB 데이터시트(PDF) 155 Page - STMicroelectronics |
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STM32H750VB 데이터시트(HTML) 155 Page - STMicroelectronics |
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155 / 335 page  DS12556 Rev 5 155/334 STM32H750VB STM32H750ZB STM32H750IB STM32H750XB Electrical characteristics (rev Y) 311 Figure 33. SDRAM write access waveforms Table 79. LPSDR SDRAM read timings(1) 1. Guaranteed by characterization results. Symbol Parameter Min Max Unit tW(SDCLK) FMC_SDCLK period 2Tfmc_ker_ck ? 12Tfmc_ker_ck + 0.5 ns tsu(SDCLKH_Data) Data input setup time 2 - th(SDCLKH_Data) Data input hold time 1.5 - td(SDCLKL_Add) Address valid time - 2.5 td(SDCLKL_SDNE) Chip select valid time - 2.5 th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS SDNRAS valid time - 0.5 th(SDCLKL_SDNRAS) SDNRAS hold time 0 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5 th(SDCLKL_SDNCAS) SDNCAS hold time 0 - MS32752V2 Row n Col1 FMC_SDCLK FMC_A[12:0] FMC_SDNRAS FMC_SDNCAS FMC_SDNWE FMC_D[31:0] FMC_SDNE[1:0] td(SDCLKL_AddR) td(SDCLKL_AddC) th(SDCLKL_AddR) th(SDCLKL_AddC) td(SDCLKL_SNDE) td(SDCLKL_Data) th(SDCLKL_Data) Col2 Coli Coln Data2 Datai Datan Data1 th(SDCLKL_SNDE) td(SDCLKL_NRAS) td(SDCLKL_NCAS) th(SDCLKL_NCAS) th(SDCLKL_NRAS) td(SDCLKL_NWE) th(SDCLKL_NWE) FMC_NBL[3:0] td(SDCLKL_NBL) |
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