STM32MP153A datasheet(129/256 Pages) STMICROELECTRONICS

129 / 256 page

DS12502 Rev 6

129/256

STM32MP153A/D

Electrical characteristics

234

6.3.4

Embedded reference voltage

The parameters given in Table 16, Table 17 are derived from tests performed under ambient

temperature and VDD supply voltage conditions summarized in Table 13: General operating

conditions.

VPVDCORE_1(5)

Digital core domain supply

voltage (VDDCORE) detector

threshold 1 (LPLV_Stop)

Falling edge

0.71

0.755

0.8

Vhyst_VDDCORE

Hysteresis of Digital core

domain supply voltage

(VDDCORE) detector

tVDDCORETEMPO

Tempo on VPVDCORE_0 at

rising edge of VDDCORE to

ensure that VDDCORE is fully

established

200

340

550

µs

tSEL_VDDCORETE

MPO

Tempo on VPVDCORE_1 at rising

edge of VDDCORE to ensure that

VDDCORE is fully established on

exit of LPLV-Stop mode

234

380

606

µs

IVDD_VDDCOREVM

(1)

VDDCORE Voltage Monitoring

consumption on VDD

1.7

2.6

4.2

µA

USB_VTH

USB Threshold voltage

1.21

1. Guaranteed by design.

2. No hysteresis when using PVD_IN pin.

3. BOR0 is enabled in all modes and its consumption is therefore included in the supply current characteristics tables.

4. During the first rising edge of VDDCORE, the slope should be less than 2 ms/V to ensure VDDCORE is fully established before

the end of the tVDDCORETEMPO.

5. When exiting from LPLV-Stop mode to RUN mode the rising slope for VDDCORE should be less than 1 ms/V to ensure

VDDCORE is fully established before the end of the tVDDCORETEMPO.

Table 15. Embedded reset and power control block characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 16. Embedded reference voltage

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VREFINT

Internal reference voltages

-40 °C < TJ < 125 °C

1.175

1.210

1.241

tS_vrefint(1)(2)

ADC sampling time when

reading the internal reference

voltage

4.3

µs

tS_vbat(1)

VBAT sampling time when

reading the internal VBAT

reference voltage

9.8

tstart_vrefint

Start time of reference voltage

buffer when ADC is enable

0.8

4.6

Irefbuf(2)

Reference Buffer consumption

for ADC

VDDA = 3.3 V

9.1

13.6

27.7

µA

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