DVR datasheet(174/416 Pages) MICROCHIP

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PIC24FJ256GA705 FAMILY

DS30010118D-page 174

 2016-2018 Microchip Technology Inc.

FIGURE 15-1:

OUTPUT COMPARE x BLOCK DIAGRAM (16-BIT MODE)

15.2

Compare Operations

In Compare mode (Figure 15-1), the output compare

module can be configured for Single-Shot or Continu-

ous mode pulse generation. It can also repeatedly

toggle an output pin on each timer event.

To set up the module for compare operations:

Configure the OCx output for one of the

available Peripheral Pin Select pins if available

on the OCx module you are using. Otherwise,

configure the dedicated OCx output pins.

Calculate the required values for the OCxR and

(for Double Compare modes) OCxRS Duty

Cycle registers:

Determine the instruction clock cycle time.

Take into account the frequency of the

external clock to the timer source (if one is

used) and the timer prescaler settings.

Calculate the time to the rising edge of the

output pulse relative to the timer start value

(0000h).

Calculate the time to the falling edge of the

pulse based on the desired pulse width and

the time to the rising edge of the pulse.

Write the rising edge value to OCxR and the

falling edge value to OCxRS.

Set the Timer Period register, PRy, to a value

equal to or greater than the value in OCxRS.

Set the OCM<2:0> bits for the appropriate

compare operation (= 0xx).

For Trigger mode operations, set OCTRIG to

enable Trigger mode. Set or clear TRIGMODE

to configure Trigger mode operation and

TRIGSTAT to select a hardware or software

trigger. For Synchronous mode, clear OCTRIG.

Set the SYNCSEL<4:0> bits to configure the

Trigger or Sync source. If free-running timer

operation is required, set the SYNCSELx bits to

‘00000’ (no Sync/Trigger source).

Select the time base source with the

OCTSEL<2:0> bits. If necessary, set the TON bit

for the selected timer, which enables the com-

pare time base to count. Synchronous mode

operation starts as soon as the time base is

enabled; Trigger mode operation starts after a

Trigger source event occurs.

OCxR and

Comparator

OCxTMR

OCxCON1

OCxCON2

OCx Interrupt

OCx Pin(1)

OCxRS

Comparator

Match Event

Trigger and

Sync Logic

Clock

Select

Increment

Reset

OCx Clock

Sources

Trigger and

Sync Sources

Reset

Match Event

OCFA/OCFB(2)

OCTSEL<2:0>

SYNCSEL<4:0>

TRIGSTAT

TRIGMODE

OCTRIG

OCM<2:0>

OCINV

OCTRIS

FLTOUT

FLTTRIEN

FLTMD

ENFLT<2:0>

OCFLT<2:0>

Note 1:

The OCx outputs must be assigned to an available RPn pin before use. See Section 11.5 “Peripheral Pin

Select (PPS)” for more information.

The OCFA/OCFB Fault inputs must be assigned to an available RPn/RPIn pin before use. See Section 11.5

“Peripheral Pin Select (PPS)” for more information.

DCB<1:0>

OCx Output and

Fault Logic

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