D301 datasheet(328/416 Pages) MICROCHIP

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PIC24FJ256GA705 FAMILY

DS30010118D-page 328

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HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER

R/W-0

U-0

R/W-0

U-0

R/W-0

HS/HC/R-0

HLVDEN

—LSIDL

—

VDIR

BGVST

IRVST

LVDEVT(2)

bit 15

bit 8

U-0

R/W-0

—

HLVDL3

HLVDL2

HLVDL1

HLVDL0

bit 7

bit 0

Legend:

HS = Hardware Settable bit

HC = Hardware Clearable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

HLVDEN: High/Low-Voltage Detect Power Enable bit

1 = HLVD is enabled

0 = HLVD is disabled

bit 14

Unimplemented: Read as ‘0’

bit 13

LSIDL: HLVD Stop in Idle Mode bit

1 = Discontinues module operation when device enters Idle mode

0 = Continues module operation in Idle mode

bit 12

Unimplemented: Read as ‘0’

bit 11

VDIR: Voltage Change Direction Select bit

1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>)

0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>)

bit 10

BGVST: Band Gap Voltage Stable Flag bit

1 = Indicates that the band gap voltage is stable

0 = Indicates that the band gap voltage is unstable

bit 9

IRVST: Internal Reference Voltage Stable Flag bit

1 = Internal reference voltage is stable; the High-Voltage Detect logic generates the interrupt flag at the

specified voltage range

0 = Internal reference voltage is unstable; the High-Voltage Detect logic will not generate the interrupt

flag at the specified voltage range and the HLVD interrupt should not be enabled

bit 8

LVDEVT: Low-Voltage Event Status bit(2)

1 = LVD event is true during current instruction cycle

0 = LVD event is not true during current instruction cycle

bit 7-4

Unimplemented: Read as ‘0’

bit 3-0

HLVDL<3:0>: High/Low-Voltage Detection Limit bits

1111 = External analog input is used (input comes from the LVDIN pin)

1110 = Trip Point 1(1)

1101 = Trip Point 2(1)

1100 = Trip Point 3(1)

•

0100 = Trip Point 11(1)

00xx = Unused

Note 1:

For the actual trip point, see Section 32.0 “Electrical Characteristics”.

The LVDIF flag cannot be cleared by software unless LVDEVT = 0. The voltage must be monitored so that

the HLVD condition (as set by VDIR and HLVDL<3:0>) is not asserted.

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