D301 datasheet(342/416 Pages) MICROCHIP

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PIC24FJ256GA705 FAMILY

DS30010118D-page 342

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29.4

Watchdog Timer (WDT)

For PIC24FJ256GA705 family devices, the WDT is driven

by the LPRC Oscillator, the Secondary Oscillator (SOSC)

or the system timer. When the device is in Sleep mode,

the LPRC Oscillator will be used. When the WDT is

enabled, the clock source is also enabled.

The nominal WDT clock source from LPRC is 31 kHz.

This feeds a prescaler that can be configured for either

5-bit (divide-by-32) or 7-bit (divide-by-128) operation.

The prescaler is set by the FWPSA Configuration bit.

With a 31 kHz input, the prescaler yields a nominal

WDT Time-out (TWDT) period of 1 ms in 5-bit mode or

4 ms in 7-bit mode.

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the WDTPS<3:0> Con-

figuration bits (FWDT<3:0>), which allows the selection

of a total of 16 settings, from 1:1 to 1:32,768. Using the

prescaler and postscaler time-out periods, ranges from

1 ms to 131 seconds can be achieved.

The WDT, prescaler and postscaler are reset:

• On any device Reset

• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit

after changing the NOSCx bits) or by hardware

(i.e., Fail-Safe Clock Monitor)

• When a PWRSAV instruction is executed

(i.e., Sleep or Idle mode is entered)

• When the device exits Sleep or Idle mode to

resume normal operation

•By a CLRWDT instruction during normal execution

If the WDT is enabled, it will continue to run during

Sleep or Idle modes. When the WDT time-out occurs,

the device will wake the device and code execution will

continue from where the PWRSAV instruction was

executed. The corresponding SLEEP or IDLE

(RCON<3:2>) bits will need to be cleared in software

after the device wakes up.

The WDT Flag bit, WDTO (RCON<4>), is not auto-

matically cleared following a WDT time-out. To detect

subsequent WDT events, the flag must be cleared in

software.

29.4.1

WINDOWED OPERATION

The Watchdog Timer has an optional Fixed Window

mode of operation. In this Windowed mode, CLRWDT

instructions can only reset the WDT during the last 1/4

of the programmed WDT period. A CLRWDT instruction

executed before that window causes a WDT Reset,

similar to a WDT time-out.

Windowed WDT mode is enabled by programming the

WINDIS Configuration bit (FWDT<7>) to ‘0’.

29.4.2

CONTROL REGISTER

The WDT is enabled or disabled by the FWDTEN<1:0>

Configuration bits (FWDT<6:5>). When the Configura-

tion bits, FWDTEN<1:0> = 11, the WDT is always

enabled.

The WDT can be optionally controlled in software when

the Configuration bits, FWDTEN<1:0> = 10. When

FWDTEN<1:0> = 00, the Watchdog Timer is always

disabled. The WDT is enabled in software by setting

the SWDTEN control bit (RCON<5>). The SWDTEN

control bit is cleared on any device Reset. The software

WDT option allows the user to enable the WDT for

critical code segments and disable the WDT during

non-critical code segments for maximum power savings.

Note:

The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts

when executed.

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