CC2430-RTR1-F64Z datasheet(142/234 Pages) TI

142 / 234 page

CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 142 of 232

13.10.8 Power Management Registers

This

section

describes

the

Power

Management registers.

PCON (0x87) – Power Mode Control

Bit

Name

Reset

R/W

Description

7:2

0x00

R/W

Not used.

Not used, always read as 0.

IDLE

R0/W

Power mode control. Writing a 1 to this bit forces

CC2430 to enter

the power mode set by

SLEEP.MODE. This bit is always read as

SLEEP (0xBE) – Sleep Mode Control

Bit

Name

Reset

R/W

Description

Unused

XOSC_STB

XOSC stable status:

0 – XOSC is not powered up or not yet stable

1 – XOSC is powered up and stable

HFRC_STB

HF RCOSC stable status:

0 – HF RCOSC is not powered up or not yet stable

1 – HF RCOSC is powered up and stable

4:3

RST[1:0]

Status bit indicating the cause of the last reset. If there are multiple

resets, the register will only contain the last event.

00 – Power-on reset

01 – External reset

10 – Watchdog timer reset

OSC_PD

R/W

XOSC and HF RCOSC power down setting. The bit is cleared if

the CLKCON.OSC bit is toggled. Also, if there is a calibration in

progress and the CPU attempts to set the bit, the bit will be

updated at the end of calibration:

0 – Both oscillators powered up

1 – Oscillator not selected by CLKCON.OSC bit powered down

1:0

MODE[1:0]

R/W

Sleep mode setting:

00 – Power mode 0

01 – Power mode 1

10 – Power mode 2

11 – Power mode 3

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