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CC2430-RTR1-F64Z 데이터시트(PDF) 219 Page - Texas Instruments

부품명 CC2430-RTR1-F64Z
상세설명  A True System-on-Chip solution for 2.4 GHz IEEE 802.15.4 / ZigBee-TM
PDF  234 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
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CC2430-RTR1-F64Z 데이터시트(HTML) 219 Page - Texas Instruments

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CC2430
CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A
Page 219 of 232
Bit
Name
Reset
R/W
Description
7
-
0
R0
Reserved, read as 0.
6:0
FIFOP_THR[6:0]
0x40
R/W
Sets the number of bytes in RXFIFO that is required for
FIFOP to go high.
Table 93: Register IOCFG0 (0xDF4F)
Bit
Name
Reset
R/W
Description
7
-
0
R0
Reserved, read as 0.
6
OE_CCA
0
R/W
CCA is output on P1.7 when this bit is 1
5
IO_CCA_POL
0
R/W
Polarity of the IO_CCA signal. This bit is xor’ed with the
internal CCA signal.
4:0
IO_CCA_SEL
000000
R/W
Multiplexer setting for the CCA signal. Must be 0x00 in
order to output the CCA status.
Table 94: Register IOCFG1 (0xDF50)
Bit
Name
Reset
R/W
Description
7
-
0
R0
Reserved, read as 0.
6
OE_SFD
0
R/W
SFD is output on P1.6 when this bit is 1
5
IO_SFD_POL
0
R/W
Polarity of the IO_SFD signal. This bit is xor’ed with the
internal SFD signal.
4:0
IO_SFD_SEL
000000
R/W
Multiplexer setting for the SFD signal. Must be 0x00 in order
to output the SFD status
Table 95: Register IOCFG2 (0xDF51)
Bit
Name
Reset
R/W
Description
7:6
-
00
R0
Reserved, read as 0.
5:4
HSSD_SRC
00
R/W
Configures the HSSD interface. Only the first 4 settings
(compared to CC2420) are used.
00 : Off
01 : Output AGC status (gain setting/peak detector
status/accumulator value)
10 : Output ADC I and Q values
11 : Output I/Q after digital down mix and channel filtering
3
OE_FIFOP
0
R/W
FIFOP is output on P1.5 when this bit is 1.
2
IO_FIFOP_POL
0
R/W
Polarity of the IO_FIFOP signal. This bit is xor’ed with the
internal FIFOP signal
1
OE_FIFO
0
R/W
FIFO is output on P1.4 when this bit is 1
0
IO_FIFO_POL
0
R/W
Polarity of the IO_FIFO signal. This bit is xor’ed with the
internal FIFO signal
Table 96: Register IOCFG3 (0xDF52)



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