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AM6546 데이터시트(PDF) 213 Page - Texas Instruments

부품명 AM6546
상세설명  AM654x, AM652x Sitara™ Processors Silicon Revision 2.1
PDF  284 Pages
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7.9.5.16 MMCSD
Note
The I/O Timings provided in this section are valid only when the corresponding DLL Delays are
configured for some MMC usage modes, as described in Table 7-52.
Note
The MMCi (i = 0 to 1) controller is also referred to as MMCi.
For more details about features and additional description information on the device Multi Media Card, see the
corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
7.9.5.16.1 MMCSDi — eMMC/SD/SDIO Card Interface
MMCi interface is compliant with the SD Standard v3.01 as well as JEDEC eMMC standard v4.5 and it supports
the following SD Card and eMMC applications:
• SD Default Speed; JEDEC 3.3V Legacy SDR
• SD High speed; JEDEC 3.3V High Speed SDR
• SD UHS-I SDR12; JEDEC 1.8V Legacy SDR
• SD UHS-I SDR25; JEDEC 1.8V High Speed SDR
• SD UHS-I SDR50
• SD UHS-I SDR104; JEDEC HS200
• UHS-I DDR50; JEDEC High Speed DDR (DDR52)
Note
For more information, see section Multimedia Card/Secure Digital () Interface in the device TRM.
Table 7-51 presents the timing conditions for MMC interface.
Table 7-51. MMC Timing Conditions
PARAMETER
MIN
MAX
UNIT
INPUT CONDITIONS
SRI
Input slew rate
Default Speed; 3.3V Legacy SDR
0.26
2.64
V/ns
High Speed; 3.3V High Speed SDR
0.69
2.06
V/ns
UHS-I SDR12; 1.8V Legacy SDR
0.14
1.44
V/ns
UHS-I SDR25; 1.8V High Speed SDR
0.3
1.34
V/ns
3.3V High Speed DDR CMD
0.69
2.06
V/ns
3.3V High Speed DDR DAT
1.03
2.06
V/ns
UHS-I DDR50 CMD; 1.8V High Speed
DDR CMD
0.3
1.34
V/ns
UHS-I DDR50 CMD; 1.8V High Speed
DDR DAT
0.34
1.34
V/ns
OUTPUT CONDITIONS
CL
Output load capacitance
SDR50
1
10
pF
SDR104; HS200
1
6
pF
All other modes
1
12
pF
PCB CONNECTIVITY REQUIREMENTS
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AM6548, AM6528, AM6546, AM6526
SPRSP52B – DECEMBER 2019 – REVISED JUNE 2021
Copyright © 2022 Texas Instruments Incorporated
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