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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DRA821U4...ALM 데이터시트(PDF) 210 Page - Texas Instruments |
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DRA821U4...ALM 데이터시트(HTML) 210 Page - Texas Instruments |
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210 / 252 page  CPTS_RFT_CLK T3 T4 T5 CPTS_HWn_TS_PUSH T1 T2 Figure 7-102. CPTS Input Timing 7.9.5.17.2 Switching Characteristics for CPTS Output NO. PARAMETER DESCRIPTION MIN MAX UNIT T6 tw(TS_COMPH) NAVSS-CPTS TS_COMP, high -2.1+36P (1) ns T7 tw(TS_COMPL) NAVSS-CPTS TS_COMP, low -2.1+36P (1) ns T8 tw(TS_COMPH) CPSW-CPTS TS_COMP, high -2.1+36P (1) ns T9 tw(TS_COMPL) CPSW-CPTS TS_COMP, low -2.1+36P (1) ns T10 tw(TS_SYNCH) NAVSS-CPTS TS_SYNC, high -2.1+36P (1) ns T11 tw(TS_SYNCL) NAVSS-CPTS TS_SYNC, low -2.1+36P (1) ns T12.1 tw(TS_SYNCH) CPSW-CPTS TS_SYNC, high -2.1+36P (1) ns T13 tw(TS_SYNCL) CPSW-CPTS TS_SYNC, low -2.1+36P (1) ns T14 tw(SYNC_OUTH) TS_SYNC sourcing SYNCn_OUT, high -2.1+36P (1) ns T15 tw(SYNC_OUTL) TS_SYNC sourcing SYNCn_OUT, low -2.1+36P (1) ns T16 tw(SYNC_OUTH) GENF sourcing SYNCn_OUT, high -2.1+5P (1) ns T17 tw(SYNC_OUTL) GENF sourcing SYNCn_OUT, low -2.1+5P (1) ns (1) P = functional clock period in ns. CPTS_TS_COMP T6 T7 CPTS_TS_SYNC T8 T9 CPTS_SYNC_OUT T10 T11 Figure 7-103. CPTS Output Switching Characteristics For more information, see Navigator Subsystem (NAVSS) section in Data Movement Architecture (DMA) chapter in the device TRM. 7.9.5.18 OSPI For more details about features and additional description information on the device Octal Serial Peripheral Interface, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description. Table 7-77 represents OSPI timing conditions. Table 7-77. OSPIx Timing Conditions PARAMETER MODE MIN MAX UNIT INPUT CONDITIONS DRA821U-Q1 SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022 www.ti.com 210 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRA821U-Q1 |
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