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ST72334J2T3 데이터시트(PDF) 109 Page - STMicroelectronics

부품명 ST72334J2T3
상세설명  8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
PDF  125 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72334J2T3 데이터시트(HTML) 109 Page - STMicroelectronics

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8.6 SUPPLY, RESET AND CLOCK CHARACTERISTICS
8.6.1 Supply Manager
Recommended operating conditions
with TA=-40 to +85
oC and voltage are referred to V
SS unless otherwise specified.
8.6.2 Reset Sequence Manager
Recommended operating conditions
with TA=-40...+85
oC and 4.5V<V
DD-VSS<5.5V unless otherwise specified.
8.6.3 Multi-Oscillator, Clock Security System
Recommended operating conditions
with TA=-40 to +85
oC and voltage are referred to V
SS unless otherwise specified.
Notes:
1) LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested.
2) The VLVDhyst hysteresis is constant.
3) Data based on characterization results, not tested in production.
4) Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
lines and are not tested.
LOW VOLTAG E DETECTOR (LVD)
Symbol
Parameter
Condition s
Min
Typ 1)
Max
Unit
VLVDr
Reset release threshold
(VDD rise)
High Threshold
Med. Threshold (fOSC≤16MHz)
Low Threshold (fOSC≤8MHz)
4.30
3.90
3.35
4.50
4.05
3.45
V
VLVDf
Reset generation threshold
(VDD fall)
High Threshold
Med. Threshold (fOSC≤16MHz)
Low Threshold (fOSC≤8MHz)
3.85
3.50
3.00
4.05
3.65
3.10
4.25
3.80
3.20
VLVDhyst
VLVD Hysteresis
2)
VLVDr -VLVDf
250*
mV
IDD
LVD Supply Current
HALT mode
100
150 3)
µA
RESET SEQUENCE MANAGER (RSM)
Symbol
Parameter
Condition s
Min
Typ 4)
Max
Unit
RON
Reset weak pull-up resistance
VIN >VIH
VIN <VIL
5
40
10
80
20
160
k
Ω
tDELAYmin
Reset delay for external and
watchdog reset sources
6
30
1/fSFOSC
µs
tPULSE
External RESET pin Pulse time
20
µs
EXTERNAL CLOCK SOURCE
Symbol
Parameter
Condition s
Min
Typ
Max
Unit
VOSC1h
OSC1 input pin high level voltage
Square wave signal
with ~50% Duty Cycle
0.7xVDD
VDD
V
VOSC1l
OSC1 input pin low level voltage
VSS
0.3xVDD



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