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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32H7B0IB 데이터시트(PDF) 118 Page - STMicroelectronics |
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STM32H7B0IB 데이터시트(HTML) 118 Page - STMicroelectronics |
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118 / 205 page  Symbol Parameter Min(1) Max(1)(2) Unit td(CLKL-Data) ns FMC_D[15:0] valid data after FMC_CLK low - 3 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Tfmc_ker_ck + 0.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2 - 1. Guaranteed by characterization results. 2. At VOS1, these values are degraded by up to 5 %. NAND controller waveforms and timings Figure 34 through Figure 37 represent synchronous waveforms, and Table 82 and Table 83 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: • COM.FMC_SetupTime = 0x01 • COM.FMC_WaitSetupTime = 0x03 • COM.FMC_HoldSetupTime = 0x02 • COM.FMC_HiZSetupTime = 0x01 • ATT.FMC_SetupTime = 0x01 • ATT.FMC_WaitSetupTime = 0x03 • ATT.FMC_HoldSetupTime = 0x02 • ATT.FMC_HiZSetupTime = 0x01 • Bank = FMC_Bank_NAND • MemoryDataWidth = FMC_MemoryDataWidth_16b • ECC = FMC_ECC_Enable • ECCPageSize = FMC_ECCPageSize_512Bytes • TCLRSetupTime = 0 • TARSetupTime = 0 • Capacitive load CL = 30 pF In all timing tables, Tfmc_ker_ck is the kernel clock period. Figure 34. NAND controller waveforms for read access FMC_NWE FMC_NOE (NRE) FMC_D[15:0] tsu(D-NOE) th(NOE-D) ALE (FMC_A17) CLE (FMC_A16) FMC_NCEx td(ALE-NOE) th(NOE-ALE) STM32H7B0xB Operating conditions DS13196 - Rev 7 page 118/205 |
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