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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32H7B0IB 데이터시트(PDF) 160 Page - STMicroelectronics |
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STM32H7B0IB 데이터시트(HTML) 160 Page - STMicroelectronics |
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160 / 205 page  Figure 64. SAI master timing waveforms SAI_SCK_X SAI_FS_X(output) 1/fSCK SAI_SD_X(transmit) tv(FS) Slot n SAI_SD_X(receive) th(FS) Slot n+2 tv(SD_MT) th(SD_MT) Slot n tsu(SD_MR) th(SD_MR) Figure 65. SAI slave timing waveforms SAI_SCK_X SAI_FS_X(input) SAI_SD_X(transmit) tsu(FS) Slot n SAI_SD_X(receive) tw(CKH_X) th(FS) Slot n+2 tv(SD_ST) th(SD_ST) Slot n tsu(SD_SR) tw(CKL_X) th(SD_SR) 1/fSCK 6.3.36.6 MDIO characteristics Unless otherwise specified, the parameters given in Table 119 are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 20. General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Measurement points are done at CMOS levels: 0.5VDD • I/O compensation cell activated. • HSLV activated when VDD ≤ 2.7 V • VOS level set to VOS0 Note: At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote when applicable. STM32H7B0xB Operating conditions DS13196 - Rev 7 page 160/205 |
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