STM32H7B3AI datasheet(140/238 Pages) STMICROELECTRONICS

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Table 88. SDRAM write timings

Symbol

Parameter

Min(1)

Max(1)(2)

Unit

tw(SDCLK)

FMC_SDCLK period

2Tfmc_ker_ck – 1

2Tfmc_ker_ck+0.5

td(SDCLKL _Data)

Data output valid time

2.5

th(SDCLKL _Data)

Data output hold time

td(SDCLKL_Add)

Address valid time

td(SDCLKL_SDNWE)

SDNWE valid time

2.5

th(SDCLKL_SDNWE)

SDNWE hold time

0.5

td(SDCLKL_ SDNE)

Chip select valid time

2(3)

th(SDCLKL-_SDNE)

Chip select hold time

0.5

td(SDCLKL_SDNRAS)

SDNRAS valid time

1.5

th(SDCLKL_SDNRAS)

SDNRAS hold time

0.5

td(SDCLKL_SDNCAS)

SDNCAS valid time

1.5

td(SDCLKL_SDNCAS)

SDNCAS hold time

0.5

1. Guaranteed by characterization results.

2. At VOS1, these values are degraded by up to 5 %.

3. Using PC2_C I/O adds 4.5 ns to this timing.

Table 89. LPSDR SDRAM write timings

Symbol

Parameter

Min(1)

Max(1)(2)

Unit

tw(SDCLK)

FMC_SDCLK period

2Tfmc_ker_ck – 1

2Tfmc_ker_ck+0.5

td(SDCLKL _Data)

Data output valid time

2.5

th(SDCLKL _Data)

Data output hold time

td(SDCLKL_Add)

Address valid time

2.5

td(SDCLKL-SDNWE)

SDNWE valid time

th(SDCLKL-SDNWE)

SDNWE hold time

td(SDCLKL- SDNE)

Chip select valid time

3(3)

th(SDCLKL- SDNE)

Chip select hold time

td(SDCLKL-SDNRAS)

SDNRAS valid time

th(SDCLKL-SDNRAS)

SDNRAS hold time

td(SDCLKL-SDNCAS)

SDNCAS valid time

td(SDCLKL-SDNCAS)

SDNCAS hold time

1. Guaranteed by characterization results.

2. At VOS1, these values are degraded by up to 5 %.

3. Using PC2_C I/O adds 16.5 ns to this timing.

STM32H7B3xI

Operating conditions

DS13139 - Rev 8

page 140/238

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