STM32H7B3AI datasheet(160/238 Pages) STMICROELECTRONICS

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Symbol

Parameter

Conditions

Min(1)

Typ(1)

Max(1)

Unit

Rnetwork

R2/R1 internal resistance

values in inverting PGA

mode(3)

PGA Gain = -7

kΩ/

kΩ

70/10

PGA Gain = -15

150/10

Delta R

Resistance variation (R1 or

R2)

−15

PGA BW

PGA bandwidth for different

non inverting gain

Gain=2

GBW/2

MHz

Gain=4

GBW/4

Gain=8

GBW/8

Gain=16

GBW/16

PGA bandwidth for different

inverting gain

Gain = -1

5.00

MHz

Gain = -3

3.00

Gain = -7

1.50

Gain = -15

0.80

Voltage noise density

at 1 KHz

output loaded with 4 kΩ

140

nV/√Hz

at 10 KHz

IDDA(OPAMP)

OPAMP consumption from

VDDA

Normal mode

no Load, quiescent

mode, follower

570

1000

µA

High-speed

mode

610

1200

1. Guaranteed by design, unless otherwise specified.

2. RLOAD is the resistive load connected to VSSA or to VDDA.

3. R2 is the internal resistance between the OPAMP output and th OPAMP inverting input. R1 is the internal resistance between the OPAMP

inverting input and ground. PGA gain = 1 + R2/R1.

6.3.30

Digital filter for Sigma-Delta Modulators (DFSDM) characteristics

Unless otherwise specified, the parameters given in Table 108. DFSDM measured timing 1.62-3.6 V for DFSDM

are derived from tests performed under the ambient temperature, fPCLKx frequency and supply voltage conditions

summarized in Table 22. General operating conditions and Section 6.3.1 .

•

Output speed is set to OSPEEDRy[1:0] = 10

•

Capacitive load CL = 30 pF

•

Measurement points are done at CMOS levels: 0.5VDD

•

VOS level set to VOS0

Refer to Section 6.3.16 I/O port characteristics for more details on the input/output alternate function

characteristics (DìFSDM_CKINx, DFSDM_DATINx, DFSDM_CKOUT for DFSDM).

Table 108. DFSDM measured timing 1.62-3.6 V

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fDFSDMCLK

DFSDM

clock

1.62 V < VDD < 3.6 V

(1)

MHz

fCKIN (1/

TCKIN)

Input clock

frequency

SPI mode (SITP[1:0]=0,1), External clock mode

(SPICKSEL[1:0]=0),

20(2)

SPI mode (SITP[1:0]=0,1), Internal clock mode

(SPICKSEL[1:0]≠0)

20(2)

fCKOUT

Output

clock

frequency

1.62 < VDD < 3.6 V

DuCyCKOUT

Output

clock

frequency

duty cycle

1.62 < VDD < 3.6 V

Even

division,CKOUTDIV[7:0]

= n, 1, 3, 5, ...

STM32H7B3xI

Operating conditions

DS13139 - Rev 8

page 160/238

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