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STM32U545NET6QTR 데이터시트(PDF) 189 Page - STMicroelectronics |
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STM32U545NET6QTR 데이터시트(HTML) 189 Page - STMicroelectronics |
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189 / 283 page ![]() DS14216 Rev 1 189/283 STM32U545xx Electrical characteristics 258 Figure 27. AC timing diagram for high-speed external clock source (digital mode) VHSEH OSC_IN input pin high-level voltage Digital mode (HSEBYP = 1, HSEEXT = 1) - 0.7 × VDD -VDD V VHSEL OSC_IN input pin low level voltage -VSS -0.3 × VDD tw(HSEH) tw(HSEL) OSC_IN high or low time Voltage scaling range 1, 2, 3 7- - ns Voltage scaling range 4 18 - - DuCyHSE OSC_IN duty cycle - 45 - 55 % VHSE_ext_ PP OSC_IN peak-to-peak amplitude Analog mode (HSEBYP = 1, HSEEXT = 0) - 0.2 - 2/3 VDD V VHSE_ext OSC_IN input range - 0 - VDD tr(HSE), tf(HSE) OSC_IN rise and fall time - 0.05 / fHSE_ext - 0.3 / fHSE_ext ns 1. Specified by design. Not tested in production. 2. Only for Analog mode. No minimum value in digital mode. Table 77. High-speed external user clock characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit MSv67850V3 VHSEH 70% 30% THSE t VHSEL tw(HSEH) tw(HSEL) VHSE |
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