HC705MC4GRSSLASHD datasheet(110/180 Pages) NXP

110 / 180 page

Pulse Width Modulator

MC68HC705MC4 — Rev. 2.0

Pulse Width Modulator

10.6 PWM during Resets

The PWM subsystem has two types of resets. One is a hardware reset

denoted by RESET. The other is a PWM reset denoted by PRESET.

After a RESET, the user should write to the data registers RATE, CTL-B,

then CTL-A (in that order). This will avoid an erroneous duty cycle from

being driven on any of the selected PWM port pins.

To save power, a PRESET condition is possible by clearing the MEB bit

and the CSB[3:1] bits in CTL-B, then the MEA bit and the CSA[3:1] bits

in CTL-A. This disables the PWM subsystem, resets the 8-bit counters,

resets the clock generator, and sets the port pins to the state defined by

the respective port data registers and data direction registers. PRESET

preserves the value of the PWMx-D registers written to them before the

PRESET condition. Activating the PWM after a PRESET will commence

operation of these preserved values.

The data registers are unaffected by RESET. The CTL-x registers are

cleared by RESET.

Address:

$0012

Bit 7

654321

Bit 0

Read:

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Write:

Reset:

Unaffected by Reset

Figure 10-14. PWMB-D Data Register (PWMB-D)

Address:

$0013

Bit 7

654321

Bit 0

Read:

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Write:

Reset:

Unaffected by Reset

Figure 10-15. PWMB-I Data Register (PWMB-I)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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