| 전자부품 데이터시트 검색엔진 |
|
STM32H7 데이터시트(PDF) 167 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STM32H7 데이터시트(HTML) 167 Page - STMicroelectronics |
|
167 / 357 page ![]() DS12110 Rev 10 167/357 STM32H742xI/G STM32H743xI/G Electrical characteristics (rev Y) 320 Figure 38. Quad-SPI timing diagram - SDR mode Figure 39. Quad-SPI timing diagram - DDR mode Table 85. QUADSPI characteristics in DDR mode(1) Symbol Parameter Conditions Min Typ Max Unit Fck1/t(CK) QUADSPI clock frequency 2.7 V<VDD<3.6 V CL=20 pF -- 100 MHz 1.62 V<VDD<3.6 V CL=15 pF -- 100 tw(CKH) QUADSPI clock high and low time - TCK/2 –0.5 - TCK/2 ns tw(CKL) TCK/2 - TCK/2+0.5 tsr(IN), tsf(IN) Data input setup time 2.7 V ≤ VDD < 3.6 V 3 - - 1.62 V ≤ VDD < 3.6 V 1 - - thr(IN), thf(IN) Data input hold time 2.7 V ≤ VDD < 3.6 V 1 - - 1.62 V ≤ VDD < 3.6 V 1.5 - - tvr(OUT), tvf(OUT) Data output valid time DHHC=0 - 3.5 4 DHHC=1 Pres=1, 2... -TCK/4+3.5 TCK/4+4 thr(OUT), thf(OUT) Data output hold time DHHC=0 3 - - DHHC=1 Pres=1, 2... TCK/4+3 - - 1. Guaranteed by characterization results. MSv36878V1 Data output D0 D1 D2 Clock Data input D0 D1 D2 t(CK) tw(CKH) tw(CKL) tr(CK) tf(CK) ts(IN) th(IN) tv(OUT) th(OUT) MSv36879V3 Data output IO0 IO2 IO4 Clock Data input IO0 IO2 IO4 t(CLK) tw(CLKH) tw(CLKL) tr(CLK) tf(CLK) tsf(IN) thf(IN) tvf(OUT) thr(OUT) IO1 IO3 IO5 IO1 IO3 IO5 tvr(OUT) thf(OUT) tsr(IN) thr(IN) |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |