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74HCT393D-Q100 데이터시트(PDF) 8 Page - Nexperia B.V. All rights reserved

부품명 74HCT393D-Q100
상세설명  Dual 4-bit binary ripple counter
PDF  1 Pages
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제조업체  NEXPERIA [Nexperia B.V. All rights reserved]
홈페이지  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved

74HCT393D-Q100 데이터시트(HTML) 8 Page - Nexperia B.V. All rights reserved

  74HCT393D-Q100 Datasheet HTML 1Page - Nexperia B.V. All rights reserved  
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Nexperia
74HC393-Q100; 74HCT393-Q100
Dual 4-bit binary ripple counter
25 °C
-40 °C to
+85 °C
-40 °C to
+125 °C
Symbol Parameter
Conditions
Min
Typ
Max
Min
Max
Min
Max
Unit
see Fig. 9
VCC = 2.0 V
6
30
-
5
-
4
-
MHz
VCC = 4.5 V
30
90
-
24
-
20
-
MHz
VCC = 5 V; CL = 15 pF
-
99
-
-
-
-
-
MHz
fclk(max) maximum
clock
frequency
VCC = 6.0 V
35
107
-
28
24
-
MHz
CPD
power
dissipation
capacitance
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
[3]
-
23
-
-
-
-
-
pF
74HCT393-Q100
nCP to nQ0; see Fig. 9
[1]
VCC = 4.5 V
-
15
25
-
31
-
38
ns
VCC = 5 V; CL = 15 pF
-
20
-
-
-
-
-
ns
nQx to nQ(x+1); see Fig. 9
[1]
VCC = 4.5 V
-
6
10
-
13
-
15
ns
tpd
propagation
delay
VCC = 5 V; CL = 15 pF
-
6
-
-
-
-
-
ns
nMR to nQx; see Fig. 10
VCC = 4.5 V
-
18
32
-
40
-
48
ns
tPHL
HIGH to LOW
propagation
delay
VCC = 5 V; CL = 15 pF
-
15
-
-
-
-
-
ns
Qn; see Fig. 9
[2]
tt
transition time
VCC = 4.5 V
-
7
15
-
19
-
22
ns
nCP HIGH or LOW; see Fig. 9
VCC = 4.5 V
19
11
-
24
-
29
-
ns
nMR HIGH; see Fig. 10
tW
pulse width
VCC = 4.5 V
16
6
-
20
-
24
-
ns
nMR to nCP; see Fig. 10
trec
recovery time
VCC = 4.5 V
5
0
-
5
-
5
-
ns
see Fig. 9
VCC = 4.5 V
27
48
-
22
-
18
-
MHz
fclk(max) maximum
clock
frequency
VCC = 5 V; CL = 15 pF
-
53
-
-
-
-
-
MHz
CPD
power
dissipation
capacitance
CL = 50 pF; f = 1 MHz;
VI = GND to VCC - 1.5 V
[3]
-
25
-
-
-
-
-
pF
[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC 2 × fo) = sum of outputs.
74HC_HCT393_Q100
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 3 — 22 October 2021
8 / 16



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