CS5535 datasheet(174/555 Pages) NSC

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Flash Controller Functional Description (Continued)

4.18.3.2 NAND

The NAND Flash interface has three external timings that are controlled by nine timing registers. The timing parameters are

described in Table 4-37 and illustrated in Figures 4-59 through 4-61.

Figure 4-59. NAND Flash Command/Address Timing

Table 4-37. NAND Flash External Timing Parameters

Symbol

Description

tCS

Control Setup Time: The setup time from the toggle of the control signals to the falling edge of WE#.

tCP

Control Pulse Width: The WE# active pulse width in the Command/Address phase.

Note that the command/address byte is put on the I/O bus at the same time that the WE# is asserted.

tCH

Control Hold Time: The hold time from the rising edge of WE# to the toggle of the control signals.

Note that the I/O bus is turned off when the tCH expires.

tWS

Data Write Setup Time: This timing is just for the internal state machine; no external reference point.

Can be set to 0 if the setup time is not needed.

tWP

Data Write Pulse Width: The WE# active pulse width in the data write phase.

Note that the data byte is put on the I/O bus at the same time that WE# is asserted; no external reference

point. Can be set to 0 if the hold time is not needed.

tRP

Data Read Pulse Width: The RE# active pulse width in the data read phase.

tRH

Data Read Hold Time: This timing is just for the internal state machine; no external reference point.

Can be set to 0 if the hold time is not needed.

tCS

tCH

tCP

tCH

Command / Address

X+1

Z+1

WE#

Z+2

CTLR_BUSY

I/O[7:0]

Note:

CTLR_BUSY is bit 2 of the NAND Status register (Flash Memory Offset 810h or Flash I/O Offset 06h).

CS5535 데이터시트(PDF) 174 Page - National Semiconductor (TI)

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