CS5535 datasheet(218/555 Pages) NSC

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218

Revision 0.8

GLPCI_SB Register Descriptions (Continued)

5.2.1.5

GeodeLink Device Power Management MSR (GLPCI_GLD_MSR_PM)

MSR Address

51000004h

Type

R/W

Reset Value

00000000_00000000h

CLPCI_GLD_MSR_PM Register Map

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

RSVD

MODEA

RSVD

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

87654321

RSVD

MODE2

MODE1

MODE0

GLPCI_GLD_MSR_PM Bit Descriptions

Bit

Name

Description

63:50

RSVD (RO)

Reserved (Read Only). Returns 0.

49:48

IOMODEA

I/O Mode A Control. These bits determine how the associated PCI inputs and outputs

will behave when the PMC asserts two internal signals that are controlled by PMS I/O

Offset 20h and 0Ch. The list of affected signals is given in Table 3-11 "Sleep Driven PCI

Signals" on page 71.

00: No gating of I/O cells during a Sleep sequence (Default).

01: During a power management Sleep sequence, force inputs to their non-asserted

state when PM_IN_SLPCTL is enabled.

10: During a power management Sleep sequence, force inputs to their non-asserted

state when PM_IN_SLPCTL is enabled, and park (force) outputs low when

PM_OUT_SLPCTL is enabled.

11: Immediately and unconditionally, force inputs to their not asserted state, and park

(force) outputs low.

47:35

RSVD (RO)

Reserved (Read Only). Returns 0.

34:32

RSVD

Reserved. Write as read.

31:6

RSVD (RO)

Reserved (Read Only). Returns 0.

5:4

PMODE2

Power Mode 2. Power mode for PCI-fast clock domain.

00: Disable clock gating. Clocks are always on.

01: Enable active hardware clock gating. Clock goes off whenever this module’s circuits

are not busy.

10: Reserved.

11: Reserved.

3:2

PMODE1

Power Mode 1. Power mode for PCI clock domain.

00: Disable clock gating. Clocks are always on.

01: Enable active hardware clock gating. Clock goes off whenever this module’s circuits

are not busy.

10: Reserved.

11: Reserved.

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