CS5535 datasheet(227/555 Pages) NSC

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GLPCI_SB Register Descriptions (Continued)

5.2.3.4

PCI Configuration Space Header Byte C-F (GLPCI_PCI_HEAD_BYTEC-F)

5.2.3.5

PCI MSR Control (GLPCI_PMCTRL)

PCI Index

0Ch

Type

Reset Value

00000000h

GLPCI_PCI_HEAD_BYTC-F Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

PCI_BIST

PCI_HEADER

PCI_LTNCY_TMR

PCI_CACHE

GLPCI_PCI_HEAD_BYTEC-F Bit Descriptions

Bit

Name

Description

31:24

PCI_BIST

PCI BIST Register (Read Only). Not implemented.

23:16

PCI_HEADER

PCI Header Type Byte (Read Only). This register defines the format of this header.

This header is of type format 0, that is, this byte contains all zeroes.

16:8

PCI_LTNCY_TMR

PCI Latency Timer Register (Read Only). Not implemented. Writing these bits have

no effect.

7:0

PCI_CACHE

PCI Cache Line Size Register (Read Only). Not implemented. Writing these bits have

no effect.

PCI Index

F0h

Type

R/W

Reset Value

00000001h

GLPCI_PMCTRL Register Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

7654

321

RSVD

GLPCI_PMCTRL Bit Descriptions

Bit

Name

Description

31:1

RSVD (RO)

Reserved (Read Only). Returns 0.

0MSR_EN

MSR Enable. Set to 1 to enable access to Model Specific Registers (MSRs).

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