| 전자부품 데이터시트 검색엔진 |
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CS5535 데이터시트(PDF) 282 Page - National Semiconductor (TI) |
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CS5535 데이터시트(HTML) 282 Page - National Semiconductor (TI) |
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282 / 555 page ![]() www.national.com 282 Revision 0.8 USB Register Descriptions (Continued) 5.5.4.6 Host Controller Interrupt Disable (USBC_HcInterruptDisable) Writing a 1 to a bit in this register clears the corresponding bit, while writing a 0 leaves the bit unchanged. USB Memory Offset 14h Type HCD: HC: R/W RO Reset Value 00000000h USBC_HcInterruptDisable Register Map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 98 7654321 0 RSVD USBC_HcInterruptDisable Bit Descriptions Bit Name HCD HC Description 31 MasterInterrupt Enable R/W RO Master Interrupt Disable. Global interrupt disable. A write of 1 disables all interrupts. 30 Ownership ChangeEnable R/W RO Ownership Change Disable. 0: Ignore. 1: Disable interrupt generation due to Ownership Change. 29:7 RSVD R/W RO Reserved. Read/write 0s. 6 RootHubStatus ChangeEnable R/W RO Root Hub Status Change Disable. 0: Ignore. 1: Disable interrupt generation due to Root Hub Status Change. 5 FrameNumber OverflowEnable R/W RO Frame Number Overflow Disable. 0: Ignore. 1: Disable interrupt generation due to Frame Number Overflow. 4 Unrecoverable ErrorEnable R/W RO Unrecoverable Error Disable. This event is not implemented. All writes to this bit will be ignored. 3 Resume DetectedEnable R/W RO Resume Detected Disable. 0: Ignore. 1: Disable interrupt generation due to Resume Detected. 2StartOfFrame Enable R/W RO Start Of Frame Disable. 0: Ignore. 1: Disable interrupt generation due to Start of Frame. 1 WritebackDone HeadEnable R/W RO Writeback Done Head Disable. 0: Ignore. 1: Disable interrupt generation due to Writeback Done Head. 0 Scheduling OverrunEnable R/W RO Scheduling Overrun Disable. 0: Ignore. 1: Disable interrupt generation due to Scheduling Overrun. |
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