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CS5535 데이터시트(PDF) 342 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 CS5535
상세설명  Geode??CS5535 I/O Companion Multi-Function South Bridge
PDF  555 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

CS5535 데이터시트(HTML) 342 Page - National Semiconductor (TI)

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342
Revision 0.8
PIC Register Descriptions (Continued)
5.9.2.6
Operation Command Word 1 / Interrupt Mask (PIC_OCW1/IMR)
5.9.2.7
Operation Command Word 2 (PIC_OCW2)
PIC_ICW4 Bit Descriptions
Bit
Name
Description
7:5
RSVD
Reserved. Write to 0.
4
SPEC_NST
Reserved (Special Fully Nested Mode). Write to 0.
3:2
RSVD
Reserved. Write to 0.
1AUTO_EOI
Auto End of Interrupt. This feature is present, but is not recommended for use. When
set to 1, this bit causes the PIC to automatically issue an End of Interrupt internally,
immediately after each Interrupt Acknowledge from the CPU. When cleared to 0 (the
default), it requires software action (writing to the OCW2 register) to signal End of Inter-
rupt.
0: Normal EOI.
1: Auto EOI (not recommended).
0
RSVD
Reserved. Write to 1 (8086/8088 mode).
I/O Port
Master: 021h
Slave:
0A1h
Type
R/W
Reset Value
00h
PIC_OCW1/IMR Register Map
76
54
32
10
IRQ7_15M
IRQ6_14M
IRQ5_13M
IRQ4_12M
IRQ3_11M
IRQ2_10M
IRQ1_9M
IRQ0_8M
PIC_OCW1/IMR Bit Descriptions
Bit
Name
Description
7
IRQ7_15M
IRQ7 / IRQ15 Mask. 0: Not Masked; 1: Masked.
6
IRQ6_14M
IRQ6 / IRQ14 Mask. 0: Not Masked; 1: Masked.
5
IRQ5_13M
IRQ5 / IRQ13 Mask. 0: Not Masked; 1: Masked.
4
IRQ4_12M
IRQ4 / IRQ12 Mask. 0: Not Masked; 1: Masked.
3
IRQ3_11M
IRQ3 / IRQ11 Mask. 0: Not Masked; 1: Masked.
2
IRQ2_10M
IRQ2 / IRQ10 Mask. 0: Not Masked; 1: Masked.
1
IRQ1_9M
IRQ1 / IRQ9 Mask. 0: Not Masked; 1: Masked.
0
IRQ0_8M
IRQ0 / IRQ8 Mask. 0: Not Masked; 1: Masked.
I/O Port
Master: 020h
Slave:
0A0h
Type
WO
Reset Value
00h
PIC_OCW2 Register Map
76
54
32
10
ROT_EOI
00
IRQ



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