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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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CS5535 데이터시트(PDF) 387 Page - National Semiconductor (TI) |
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CS5535 데이터시트(HTML) 387 Page - National Semiconductor (TI) |
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387 / 555 page  Revision 0.8 387 www.national.com UART/IR Controller Register Descriptions (Continued) 5.12.5.6 RX_FIFO Current Level Register (RXFLV) RXFLV returns the number of bytes in the RX_FIFO. It can be used for software debugging. 5.12.6 Bank 3 Register Descriptions The bit formats for the registers in Bank 3 are summarized in Table 5-41. Detailed descriptions of each register follow. 5.12.6.1 Module Identification and Revision ID Register (MRID) MRID identifies the revision of the module. When read, it returns the module ID and revision level in the format 0xh, where x indicates the revision number. I/O Offset 07h Type RO Reset Value 00h RXFLV Register Map 76 54 32 10 RSVD RFL[5:0] RXFLV Bit Descriptions Bit Name Description 7:6 RSVD Reserved. Return 0s. 5:0 RFL[5:0] Number of Bytes in RX_FIFO. These bits specify the number of bytes in the RX_FIFO. Note: The contents of TXFLV and RXFLV are not frozen during CPU reads. Therefore, invalid data could be returned if the CPU reads these registers during normal transmitter and receiver operation. To obtain correct data, the software should perform three consecutive reads and then take the data from the second read if the first and second reads yield the same result. It can also be taken from the third read if the first and second reads yield different results. Table 5-41. Bank 3 Bit Map Register Bits I/O Offset Name 7654 3210 00h MRID MID[3:0] RID[3:0] 01h SH_LCR RSVD SBRK STKP EPS PEN STB WLS1 WLS0 02h SH_FCR RXFTH[1:0] TXFTH[1:0] RSVD TXSR RXSR FIFO_EN 03h BSR BKSE BSR[6:0] 04h-07h RSVD RSVD I/O Offset 00h Type RO Reset Value 0xh MRID Register Map 76 54 32 10 MID[3:0] RID[3:0] |
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