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CS5535 데이터시트(PDF) 409 Page - National Semiconductor (TI) |
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CS5535 데이터시트(HTML) 409 Page - National Semiconductor (TI) |
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409 / 555 page ![]() Revision 0.8 409 www.national.com DMA Register Descriptions (Continued) 5.13.2.8 Slave DMA Channel [3:0] Master Clear (DMA_CH3:0_MSTR_CLR) 5.13.2.9 Slave DMA Channel [3:0] Clear Mask Register (DMA_CH3:0_CLR_MSK) 5.13.2.10 Slave DMA Channel [3:0] Write Mask Register (DMA_CH3:0_WR_MSK) DMA_CH3:0_CLR_PNTR Bit Descriptions Bit Name Description 7:0 CLR_PNTR Clear Pointer. A write with any data (dummy value) resets high/low byte pointer for Channels 3:0 memory address and terminal count registers. I/O Address 00Dh Type WO Reset Value xxh DMA_CH3:0_MSTR_CLR Register Map 76543 210 MSTR_CLR (DUMMY_VAL) DMA_CH3:0_MSTR_CLR Bit Descriptions Bit Name Description 7:0 MSTR_CLR Master Clear. A write with any data (dummy value) resets the 8237 DMA controller for Channels [3:0]. I/O Address 00Eh Type WO Reset Value xxh DMA_CH3:0_CLR_MSK Register Map 76543 210 CLR_MSK (DUMMY_VAL) DMA_CH3:0_CLR_MSK Bit Descriptions Bit Name Description 7:0 CLR_MSK Clear Mask. A write with any data (dummy value) clears the mask bits for Channels [3:0]. I/O Address 00Fh Type WO Reset Value 0Fh DMA_CH3:0_WR_MSK Register Map 76543 210 RSVD CH3_MASK CH2_MASK CH1_MASK CH0_MASK |
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