CS5535 datasheet(456/555 Pages) NSC

456 / 555 page

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456

Revision 0.8

GPIO Subsystem Register Descriptions (Continued)

5.16.3.3

GPIO Event Counter (GPIO_EVNTCNT[x])

Writing to these 16-bit registers programs the counter value. Reads provide current counter value.

GPIO Event Counter 0 (GPIO_EVNTCNT0)

GPIO Event Counter 1 (GPIO_EVNTCNT1)

GPIO Event Counter 2 (GPIO_EVNTCNT2)

GPIO Event Counter 3 (GPIO_EVNTCNT3)

GPIO Event Counter 4 (GPIO_EVNTCNT4)

GPIO Event Counter 5 (GPIO_EVNTCNT5)

GPIO Event Counter 6 (GPIO_EVNTCNT6)

GPIO Event Counter 7 (GPIO_EVNTCNT7)

GPIO I/O Offset

54h

Type

R/W

Reset Value

0000h

GPIO I/O Offset

5Ch

Type

R/W

Reset Value

0000h

GPIO I/O Offset

64h

Type

R/W

Reset Value

0000h

GPIO I/O Offset

6Ch

Type

R/W

Reset Value

0000h

GPIO I/O Offset

74h

Type

R/W

Reset Value

0000h

GPIO I/O Offset

7Ch

Type

R/W

Reset Value

0000h

GPIO I/O Offset

D4h

Type

R/W

Reset Value

0000h

GPIO I/O Offset

DCh

Type

R/W

Reset Value

0000h

GPIO_EVNTCNT[x] Register Map

987

6543

210

EVENT_COUNT

GPIO_EVNTCNT_[x] Bit Descriptions

Bit

Name

Description

15:0

EVENT_COUNT

Event Counter Status. Direct access to the counter’s state is provided via this register

and may be read at any time to determine the current value of the counter. This register

may also be written to at any time, thereby jamming the counter state forward or back-

ward from the current count. Hardware provisions exist to ensure accurate readings

even if a counter edge is in process.

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